Editing Wafer (electronics)

{{Short description|Thin slice of semiconductor used for the fabrication of integrated circuits}}
{{Multiple image
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|image1=Siliziumwafer.JPG{{!}}polished 12" and 6" silicon wafers
|image2=ICC 2008 Poland Silicon Wafer 1 edit.png{{!}}VLSI microcircuits fabricated on a 12-inch wafer
|image3=Wafers on the conveyor (3347741252).jpg{{!}}Solar wafers on a conveyor
|image4=Solar World wafer (3347743800).jpg{{!}}Completed solar wafer
|footer=<div>
<!--Modie Wafer-->
* Top left: polished 12" and 6" silicon wafers. Their crystallographic orientation is marked by notches and flat cuts. Top right: [[VLSI]] microcircuits fabricated on a {{convert|12|in|mm|adj=on}} silicon wafer, before [[wafer dicing|dicing]] and [[Integrated circuit packaging|packaging]].
* Bottom left: A 3D rendering of solar wafers on a conveyor. Bottom right: completed solar wafers</div>
}}

In [[electronics]], a '''wafer''' (also called a '''slice''' or '''substrate''')<ref>
{{cite book
 | title = Comprehensive Dictionary of Electrical Engineering
 | edition = 2nd
 | first = Phillip A. | last = Laplante
 | location = Boca Raton, Florida | publisher = [[CRC Press]]
 | date = 2005
 | isbn = 978-0-8493-3086-5
 | chapter = Wafer
 | page = 739
 | chapter-url = https://books.google.com/books?id=zoAqBgAAQBAJ&q=wafer&pg=PA739
 }}</ref> is a thin slice of [[semiconductor]], such as a [[crystalline silicon]] (c-Si, silicium), used for [[Semiconductor device fabrication|the fabrication]] of [[integrated circuit]]s and, in [[photovoltaics]], to manufacture [[solar cell]]s.

The wafer serves as the [[substrate (materials science)|substrate]] for [[microelectronic]] devices built in and upon the wafer. It undergoes many [[microfabrication]] processes, such as [[doping (semiconductor)|doping]], [[ion implantation]], [[Etching (microfabrication)|etching]], [[thin-film deposition]] of various materials, and [[Photolithography|photolithographic]] patterning. Finally, the individual microcircuits are separated by [[wafer dicing]] and [[Integrated circuit packaging|packaged]] as an integrated circuit.

== History ==
{{expand section|date=January 2015}}
{{see also|List of silicon producers}}

In the semiconductor industry, the term wafer appeared in the 1950s to describe a thin round slice of semiconductor material, typically [[germanium]] or silicon. The round shape characteristic of these wafers comes from [[Boule (crystal)|single-crystal ingots]] usually produced using the [[Czochralski method]]. Though, silicon wafers were first introduced in the 1940s.<ref>{{cite journal |author=Reinhard Voelkel | title=Wafer-scale micro-optics fabrication | journal=Advanced Optical Technologies | year=2012 | volume=1 | issue=3 | page=135 | doi=10.1515/aot-2012-0013| bibcode=2012AdOT....1..135V | s2cid=137606531 | doi-access=free }}</ref><ref>{{cite book |author1=T. Doi |author2=I.D. Marinescu |author3=Syuhei Kurokawa | title=Advances in CMP Polishing Technologies, Chapter 6 – Progress of the Semiconductor and Silicon Industries – Growing Semiconductor Markets and Production Areas | pages=297–304 | publisher=Elsevier | year=2012 | doi=10.1016/B978-1-4377-7859-5.00006-5}}</ref>

By 1960, silicon wafers were being manufactured in the U.S. by companies such as [[MEMC Electronic Materials|MEMC]] and [[SunEdison]]. In 1965, American engineers Eric O. Ernst, Donald J. Hurd, and Gerard Seeley, while working under [[IBM]], filed Patent US3423629A<ref>{{cite web|url=https://patents.google.com/patent/US3424629A/en|title=High capacity epitaxial apparatus and method|website=google.com}}</ref> for the first high-capacity [[epitaxy|epitaxial]] apparatus.

== Production ==

=== Formation ===
{{See also|Boule (crystal)}}
[[File:Czochralski Process.svg|thumb|326px|The [[Czochralski method]]]]

Wafers are formed of highly pure,<ref name="Semi">SemiSource 2006: A supplement to Semiconductor International. December 2005. Reference Section:
''How to Make a Chip.'' Adapted from Design News. Reed Electronics Group.</ref>
nearly defect-free single [[crystalline]] material, with a purity of 99.9999999% ([[Nine (purity)|9N]]) or higher.<ref name="Semi" />
One process for forming crystalline wafers is known as the [[Czochralski method]], invented by Polish chemist [[Jan Czochralski]]. In this process, a cylindrical [[ingot]] of high purity monocrystalline semiconductor, such as silicon or [[germanium]], called a [[Boule (crystal)|boule]], is formed by pulling a [[seed crystal]] from a [[melt (manufacturing)|melt]].<ref>{{cite book |title=Microelectronic Materials and Processes |last=Levy |first=Roland Albert |year=1989 |pages=1–2 |publisher=Springer |isbn=978-0-7923-0154-7 |url=https://books.google.com/books?id=wZPRPU6ne7UC&pg=PA248 |access-date=2008-02-23}}</ref><ref name=Grover/> Donor impurity atoms, such as [[boron]] or [[phosphorus]] in the case of silicon, can be added to the molten [[Intrinsic semiconductor|intrinsic material]] in precise amounts in order to [[Doping (semiconductor)|dope]] the crystal, thus changing it into an [[extrinsic semiconductor]] of [[N-type semiconductor|n-type]] or [[P-type semiconductor|p-type]].

The boule is then [[wikt:sliced|sliced]] with a wafer saw (a type of [[wire saw]]), machined to improve flatness, chemically etched to remove crystal damage from machining steps and finally [[polishing|polished]] to form wafers.<ref>{{cite book |last=Nishi |first=Yoshio |year=2000|title=Handbook of Semiconductor Manufacturing Technology |pages=67–71 |publisher=CRC Press |isbn=978-0-8247-8783-7 |url=https://books.google.com/books?id=Qi98H-iTgLEC&q=wafer+flat+and+notch&pg=PA70 |access-date=2008-02-25}}</ref> The size of wafers for photovoltaics is 100–200&nbsp;mm square and the thickness is 100–500&nbsp;μm.<ref>{{cite web |url=https://www.pveducation.org/pvcdrom/design-of-silicon-cells/silicon-solar-cell-parameters |title=Silicon Solar Cell Parameters |access-date=2019-06-27}}</ref> Electronics use wafer sizes from 100 to 450&nbsp;mm diameter. The largest wafers made have a diameter of 450&nbsp;mm,<ref>{{cite web|url = http://www.f450c.org/infographic/|archive-url = https://archive.today/20160105165200/http://www.f450c.org/infographic/|url-status = usurped|archive-date = January 5, 2016|title = Evolution of the Silicon Wafer|website = F450C}}</ref> but are not yet in general use.

=== Cleaning, texturing and etching ===

Wafers are cleaned with [[weak acid]]s to remove unwanted particles. There are several standard cleaning procedures to make sure the surface of a silicon wafer contains no contamination. One of the most effective methods is the [[RCA clean]].
When used for [[solar cell]]s, the wafers are textured to create a rough surface to increase surface area and so their efficiency. The generated PSG ([[phosphosilicate glass]]) is removed from the edge of the wafer in the [[etching]].<ref>{{cite web |url=http://www.omron-semi-pv.eu/en/wafer-based-pv/front-end/wet-process.html |title=Wet Process |website=Omron Industrial Automation|access-date=November 26, 2008 |archive-url=https://web.archive.org/web/20090204143516/http://www.omron-semi-pv.eu/en/wafer-based-pv/front-end/wet-process.html |archive-date=February 4, 2009  }}</ref>

== Wafer properties ==

=== Standard wafer sizes ===
==== Silicon substrate ====
Silicon wafers are available in a variety of diameters from 25.4&nbsp;mm (1&nbsp;inch) to 300&nbsp;mm (11.8&nbsp;inches).<ref name=f450c>{{cite web|title = Evolution Of Silicon Wafer {{!}} F450C|url = http://www.f450c.org/infographic/|archive-url = https://archive.today/20160105165200/http://www.f450c.org/infographic/|url-status = usurped|archive-date = January 5, 2016|website = F450C|access-date = 2015-12-17|language = en-US}}</ref><ref>{{cite web |title=Silicon Wafer |url=http://www.semiwafer.com/products/silicon.htm |access-date=2008-02-23  |archive-url=https://web.archive.org/web/20080220102757/http://www.semiwafer.com/products/silicon.htm |archive-date=2008-02-20 }}</ref> [[Semiconductor fabrication plant]]s, colloquially known as ''fabs'', are defined by the diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab using {{nowrap|300 mm}}, with a proposal to adopt {{nowrap|450 mm}}.<ref>{{cite web|url=http://www.intel.com/pressroom/archive/releases/20080505corp.htm|title=Intel, Samsung, TSMC reach agreement about 450mm tech|website=intel.com}}</ref><ref>[http://www.itrs.net/Links/2008Summer/Public Presentations/PDF/FEP.pdf ITRS Presentation (PDF)]{{Dead link|date=August 2018 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> [[Intel]], [[TSMC]], and [[Samsung]] were separately conducting research to the advent of {{nowrap|450 mm}} "[[prototype]]" (research) [[fab (semiconductors)|fab]]s, though serious hurdles remain.<ref>{{cite web |url=https://www.eetimes.com/450-mm-fab-debate-surfaces/ |title=450-mm fab debate surfaces |last=LaPedus |first=Mark |date=January 14, 2009 |website=EE Times |publisher=Aspencore |access-date=2021-05-09 |quote=As reported, Intel, TSMC and Samsung are separately pushing for the advent of 450-mm ''prototype'' fabs by 2012}}</ref>

[[File:Wafer 2 Zoll bis 8 Zoll 2.jpg|thumb|275px|{{convert|2|in|mm|adj=on}}, {{convert|4|in|mm|adj=on}}, {{convert|6|in|mm|adj=on}}, and {{convert|8|in|mm|adj=on}} wafers]]
{| class="wikitable sortable mw-collapsible" style="text-align:center"
|-
! Wafer size
! Typical thickness
! Year introduced <ref name=f450c />
! Weight per wafer
! 100&nbsp;mm<sup>2</sup> die per wafer
|-
| {{convert|1|in|mm|adj=on}}
|
| 1960
|
|
|-
| {{convert|2|in|mm|adj=on}}
| 275 [[μm]]
| 1969
|
|9
|-
| {{convert|3|in|mm|adj=on}}
| 375&nbsp;μm
| 1972
|
|29
|-
| {{convert|4|in|mm|adj=on}}
| 525&nbsp;μm
| 1976
| 10 grams <ref name="auto">{{cite web|url=http://wafercare.com/Page.aspx?id=1012|archive-url=https://web.archive.org/web/20131207002716/http://wafercare.com/Page.aspx?id=1012|archive-date=December 7, 2013|title=450 mm Wafer Handling Systems|date=December 7, 2013}}</ref>
| 56
|-
| 4.9&nbsp;inch (125&nbsp;mm)
| 625&nbsp;μm
| 1981
|
|95
|-
| 150&nbsp;mm (5.9&nbsp;inch, usually referred to as "6 inch")
| 675&nbsp;μm
| 1983
|
|144
|-
| 200&nbsp;mm (7.9&nbsp;inch, usually referred to as "8 inch")
| 725&nbsp;μm.
| 1992
| 53 grams <ref name="auto"/>
| 269
|-
| 300&nbsp;mm (11.8&nbsp;inch, usually referred to as "12 inch")
| 775&nbsp;μm
| 1999
| 125 grams<ref name="auto"/>
| 640
|-
| {{nowrap|450 mm}} (17.7&nbsp;inch) (proposed)<ref>{{cite web|url=https://www.eetimes.com/document.asp?doc_id=1169573|title=Industry agrees on first 450-mm wafer standard|first=Mark|last=LaPedus|website=EETimes}}</ref> 
| 925&nbsp;μm
| –
| 342 grams <ref name="auto"/>
| 1490
|-
| {{convert|675|mm|in|adj=on}} (theoretical)<ref>{{cite web|url=https://www.daifuku.com/solution/technology/semiconductor/|title=The Evolution of AMHS|website=www.daifuku.com|access-date=2018-12-02|archive-date=2019-04-08|archive-url=https://web.archive.org/web/20190408010203/https://www.daifuku.com/solution/technology/semiconductor/}}</ref>
| unknown
| –
| unknown
| 3427
|}
Wafers grown using materials other than silicon will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the [[mechanical strength]] of the material used; the wafer must be thick enough to support its own weight without cracking during handling. The tabulated thicknesses relate to when that process was introduced, and are not necessarily correct currently, for example the IBM BiCMOS7WL process is on 8-inch wafers, but these are only 200&nbsp;μm thick. The weight of the wafer increases with its thickness and the square of its diameter.  Date of introduction does not indicate that factories will convert their equipment immediately, in fact, many factories do not bother upgrading.  Instead, companies tend to expand and build whole new lines with newer technologies, leaving a large spectrum of technologies in use at the same time.

==== Gallium Nitride substrate ====
GaN substrate wafers typically have had their own independent timelines, parallel but far lagging silicon substrate, but ahead of other substrates.  The world's first 300 mm wafer made of GaN was announced in Sept 2024 by Infineon, suggesting in the coming future they could put into use the first factory with 300 mm GaN commercial output.<ref>https://asia.nikkei.com/Business/Tech/Semiconductors/Infineon-unveils-world-s-first-12-inch-GaN-power-chip-wafer-tech</ref>

==== SiC substrate ====
Meanwhile world's first Silicon Carbide (SiC) 200 mm wafers were announced in July 2021 by ST Microelectronics.<ref>https://newsroom.st.com/media-center/press-item.html/t4380.html</ref> It is not known if SiC 200 mm has entered volume production as of 2024, as typically the largest fabs for SiC in commercial production remain at 150 mm.

==== Silicon on sapphire ====
[[Silicon on sapphire]] is different from silicon substrate as the substrate is sapphire, while superstrate is silicon, while epitaxal layers and doping can be anything. SOS in commercial production is typically maxed out at 150 mm wafer sizes as of 2024.

==== Gallium Arsenide substrate ====
GaAs wafers tend to be 150 mm at largest, in commercial production as of 2024.<ref>https://www.3dincites.com/2024/04/the-role-of-200mm-manufacturing-in-enabling-a-1-trillion-semiconductor-industry/</ref>

==== Aluminum Nitride substrate ====
AlN tends to be 50 mm or 2 inch wafers in commercial production, while 100 mm or 4 inch wafers are [https://www.asahi-kasei.com/news/2024/e240612.html being developed as of 2024] by wafer suppliers like Asahi Kasei.  However, merely because a wafer exists commercially, does not imply in any way that processing equipment to produce chips on that wafer exists, indeed such equipment tends to lag development until paying end customer demand materializes.  Even after equipment is developed (years), it can take further years for fabs to figure out how to use the machines productively.

==== Historical increases of wafer size ====
A unit of [[wafer fabrication]] step, such as an etch step, can produce more chips proportional to the increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer area. This was the cost basis for increasing wafer size. Conversion to 300&nbsp;mm wafers from 200&nbsp;mm wafers began in early 2000, and reduced the price per die for about 30–40%.{{cn|date=December 2024}}Larger diameter wafers allow for more die per wafer.

==== Photovoltaic ====
{{expand section|date=July 2020}}
M1 wafer size (156.75&nbsp;mm) is in the process of being phased out in China as of 2020. Various nonstandard wafer sizes have arisen, so efforts to fully adopt the M10 standard (182&nbsp;mm) are ongoing. Like other semiconductor fabrication processes, driving down costs has been the main driving factor for this attempted size increase, in spite of the differences in the manufacturing processes of different types of devices.{{Citation needed|date=February 2022}}

=== Crystalline orientation ===
[[File:Silicon-unit-cell-3D-balls.png|thumb|Diamond cubic crystal structure of a silicon unit cell]]
[[File:Wafer flats convention v2.svg|thumb|Flats can be used to denote [[doping (semiconductors)|doping]] and [[crystallography|crystallographic]] orientation. Red represents material that has been removed.]]

Wafers are grown from crystal having a regular [[crystal structure]], with silicon having a [[diamond cubic]] structure with a lattice spacing of 5.430710 Å (0.5430710&nbsp;nm).<ref name="HandbookSi">{{cite book|last=O'Mara|first=William C.|url=https://books.google.com/books?id=COcVgAtqeKkC&q=Czochralski+Silicon+Crystal+Face+Cubic&pg=PA351|title=Handbook of Semiconductor Silicon Technology|publisher=William Andrew Inc.|year=1990|isbn=978-0-8155-1237-0|pages=349–352|access-date=2008-02-24}}</ref> When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the [[Miller index]] with (100) or (111) faces being the most common for silicon.<ref name=HandbookSi/>
Orientation is important since many of a single crystal's structural and electronic properties are highly [[anisotropic]]. [[Ion implantation]] depths depend on the wafer's crystal orientation, since each direction offers distinct [[Ion implantation#Ion channelling|paths]] for transport.<ref>{{cite book|last=Nishi|first=Yoshio|url=https://books.google.com/books?id=Qi98H-iTgLEC&q=wafer+flat+and+notch&pg=PA70|title=Handbook of Semiconductor Manufacturing Technology|publisher=CRC Press|location=Boca Raton, Florida|year=2000|isbn=978-0-8247-8783-7|pages=108–109|access-date=2008-02-25}}</ref>

Wafer [[cleavage (crystal)|cleavage]] typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("[[Die (integrated circuit)|die]]s") so that the billions of individual [[Electronic component|circuit elements]] on an average wafer can be separated into many individual circuits.{{Citation needed|date=February 2021}}

=== Crystallographic orientation notches ===

Wafers under 200&nbsp;mm diameter have ''flats'' cut into one or more sides indicating the [[crystallography|crystallographic]] planes of the wafer (usually a {110} face). In earlier-generation wafers a pair of flats at different angles additionally conveyed the doping type (see illustration for conventions). Wafers of 200&nbsp;mm diameter and above use a single small notch to convey wafer orientation, with no visual indication of doping type. 450 mm wafers are notchless, relying on a laser scribed structure on the wafer surface for orientation.<ref>{{cite web|last=Föll|first=Helmut|date=October 2019|title=Wafer Flats|url=http://www.tf.uni-kiel.de/matwis/amat/elmat_en/kap_5/illustr/i5_2_4.html|access-date=2008-02-23|publisher=[[University of Kiel]]}}</ref>

=== Impurity doping ===

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity [[Doping (semiconductors)|doping]] concentration between 10<sup>13</sup> and 10<sup>16</sup> atoms per cm<sup>3</sup> of [[boron]], [[phosphorus]], [[arsenic]], or [[antimony]] which is added to the melt and defines the wafer as either bulk n-type or p-type.<ref>{{cite book|last=Widmann|first=Dietrich|url=https://books.google.com/books?id=uYNn1N6YSwQC&q=Czochralski+Doping+Silicon&pg=PA39|title=Technology of Integrated Circuits|publisher=Springer|year=2000|isbn=978-3-540-66199-3|page=39|access-date=2008-02-24}}</ref> However, compared with single-crystal silicon's atomic density of 5×10<sup>22</sup> atoms per cm<sup>3</sup>, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some [[interstitial defect|interstitial]] oxygen concentration. Carbon and metallic contamination are kept to a minimum.<ref>{{cite book|last=Levy|first=Roland Albert|url=https://books.google.com/books?id=wZPRPU6ne7UC&pg=PA248|title=Microelectronic Materials and Processes|year=1989|isbn=978-0-7923-0154-7|pages=6–7, 13|publisher=Springer |access-date=2008-02-23}}</ref> [[Transition metal]]s, in particular, must be kept below parts per billion concentrations for electronic applications.<ref>{{cite book|last=Rockett|first=Angus|title=The Materials Science of Semiconductors|year=2008|isbn=978-0-387-25653-5|page=13|publisher=Springer }}</ref>

== {{Anchor|Proposed 450 mm transition}}450 mm wafers ==

=== Challenges ===
There is considerable resistance to the 450&nbsp;mm transition despite the possible productivity improvement, because of concern about insufficient return on investment.{{cn|date=December 2024}} There are also issues related to increased inter-die / edge-to-edge wafer variation and additional edge defects. 450mm wafers are expected to cost 4 times as much as 300mm wafers, and equipment costs are expected to rise by 20 to 50%.<ref>{{cite web|author=Steve Schulz |url=https://www.eetimes.com/collaborative-advantage-design-impact-of-450mm-transition/ |title=Collaborative advantage: Design impact of 450mm transition |publisher=EETimes |access-date=2022-03-08}}</ref> Higher cost semiconductor fabrication equipment for larger wafers increases the cost of 450&nbsp;mm fabs (semiconductor fabrication facilities or factories). Lithographer [[Chris Mack (scientist)|Chris Mack]] claimed in 2012 that the overall price per die for 450&nbsp;mm wafers would be reduced by only 10–20% compared to 300&nbsp;mm wafers, because over 50% of total wafer processing costs are lithography-related. Converting to larger 450&nbsp;mm wafers would reduce price per die only for process operations such as etch where cost is related to wafer count, not wafer area.{{Citation needed|date=July 2021}} Cost for processes such as lithography is proportional to wafer area, and larger wafers would not reduce the lithography contribution to die cost.<ref>{{cite web|url=http://life.lithoguru.com/index.php?itemid=253|title=Lithoguru {{!}} Musings of a Gentleman Scientist|website=life.lithoguru.com|language=en-US|access-date=2018-01-04}}</ref>

Nikon planned to deliver 450-mm lithography equipment in 2015, with volume production in 2017.<ref name="Nikon 2014-05-20">{{cite press release |title=Nikon appointing head of precision equipment business as new president |location=Japan |publisher=Nikon Corp. |agency=semiconportal |date=May 20, 2014|quote=Nikon plans to introduce 450mm wafer lithography systems for volume production in 2017. }}</ref><ref name="Nikon 2013-09-13">{{cite news |last=LaPedus |first=Mark |url=http://semiengineering.com/litho-roadmap-remains-cloudy/ |title=Litho Roadmap Remains Cloudy |work=semiengineering.com |publisher=Sperling Media Group LLC |date=2013-09-13 |access-date=July 14, 2014 |quote=Nikon planned to ship 'early learning tools' by 2015. 'As we have said, we will be shipping to meet customer orders in 2015,' said Hamid Zarringhalam, executive vice president at Nikon Precision. }}</ref> In November 2013 [[ASML Holding|ASML]] paused development of 450-mm lithography equipment, citing uncertain timing of chipmaker demand.<ref name="ASML 2013 Annual report">{{cite web|url=https://www.sec.gov/Archives/edgar/data/937966/000119312514046822/d546896d20f.htm |title=ASML 2013 Annual Report Form (20-F) |publisher=United States Securities and Exchange Commission |format=XBRL |date=February 11, 2014 |quote=In November 2013, following our customers' decision, ASML decided to pause the development of 450&nbsp;mm lithography systems until customer demand and the timing related to such demand is clear. }}</ref>

In 2012, a group consisting of [[New York (state)|New York State]] ([[SUNY Polytechnic Institute|SUNY Poly]]/[[SUNY Poly College of Nanoscale Science and Engineering|College of Nanoscale Science and Engineering]] (CNSE)), Intel, TSMC, Samsung, IBM, Globalfoundries and Nikon companies has formed a [[Public–private partnership|public-private partnership]] called Global 450mm Consortium (G450C, similar to [[SEMATECH]]) who made a 5-year plan (expiring in 2016) to develop a "cost effective wafer fabrication infrastructure, equipment prototypes and tools to enable coordinated industry transition to 450mm wafer level".<ref>{{cite web|title=G450C: a Global 450mm Consortium|url=https://www.vlsiresearch.com/g450c-a-global-450mm-consortium-PFEL1SE1H87HUYM|access-date=2021-07-26|website=VLSI Research|language=en}}</ref><ref>{{cite web|date=2013-05-17|title=The Bumpy Road To 450mm|url=https://semiengineering.com/the-bumpy-road-to-450mm/|access-date=2021-07-26|website=Semiconductor Engineering|language=en-US}}</ref> In the mid of 2014 CNSE has announced that it will reveal first fully patterned 450mm wafers at SEMICON West.<ref>{{cite web|title=World's First Fully Patterned 450mm Wafers Unveiled at SEMICON West {{!}} SUNY Polytechnic Institute|url=https://sunypoly.edu/news/worlds-first-fully-patterned-450mm-wafers-unveiled-semicon-west.html|access-date=2021-07-26|website=sunypoly.edu}}</ref> In early 2017, the G450C began to dismantle its activities over 450mm wafer research due to undisclosed reasons.<ref>{{cite web|date=2017-01-17|title=450mm Officially On Hold {{!}} 450mm.com|url=http://450mm.com/blog/2017/01/17/450mm-officially-on-hold/|access-date=2021-07-26|website=450mm|language=en-US|archive-date=2021-07-26|archive-url=https://web.archive.org/web/20210726102109/http://450mm.com/blog/2017/01/17/450mm-officially-on-hold/}}</ref><ref name="Rulison">{{cite web|last=Rulison|first=Larry|date=2017-01-10|title=Future of SUNY Poly's 450mm program in doubt|url=https://www.timesunion.com/tuplus/article/Money-dries-up-for-another-SUNY-Poly-program-10847093.php|access-date=2021-07-26|website=Times Union|language=en-US}}</ref><ref name=":0"/> Various sources have speculated that demise of the group came after charges of [[bid rigging]] made against [[Alain E. Kaloyeros]], who at the time was a chief executive at the SUNY Poly.<ref name=":0">{{cite web|last=Rulison|first=Larry|date=2017-01-14|title=NY: Demise of G450C wasn't over money|url=https://www.timesunion.com/tuplus-business/article/NY-Demise-of-G450C-wasn-t-over-money-10857261.php|access-date=2021-07-26|website=Times Union|language=en-US}}</ref><ref name="Rulison"/><ref>{{cite web|date=January 17, 2017|title=450mm Officially On Hold…|url=http://450mm.com/blog/2017/01/17/450mm-officially-on-hold/|access-date=July 26, 2021|archive-date=July 26, 2021|archive-url=https://web.archive.org/web/20210726102109/http://450mm.com/blog/2017/01/17/450mm-officially-on-hold/}}</ref> The industry realization of the fact that the 300mm manufacturing optimization is more cheap than costly 450mm transition may also have played a role.<ref name=":0" />

The timeline for 450&nbsp;mm has not been fixed. In 2012, it was expected that 450mm production would start in 2017, which never realized.<ref>{{cite web|author=Dylan McGrath |url=https://www.eetimes.com/first-450-mm-fabs-to-ramp-in-2017-says-analyst/ |title=First 450-mm fabs to ramp in 2017, says analyst |publisher=EETimes |access-date=2022-03-08}}</ref><ref>{{cite web|url=https://www.eetimes.com/construction-of-450mm-fab-well-underway/ |title=Construction of 450mm Fab 'Well Underway' |publisher=EETimes |date=2013-08-15 |access-date=2022-03-08}}</ref> Mark Durcan, then CEO of [[Micron Technology]], said in February 2014 that he expects 450&nbsp;mm adoption to be delayed indefinitely or discontinued. "I am not convinced that 450mm will ever happen but, to the extent that it does, it's a long way out in the future. There is not a lot of necessity for Micron, at least over the next five years, to be spending a lot of money on 450mm."<ref>{{cite web|last=Manners|first=David|date=2014-02-11|title=450mm May Never Happen, says Micron CEO|url=https://www.electronicsweekly.com/blogs/mannerisms/manufacturing-mannerisms/6706-2014-02/|access-date=2022-02-03|website=Electronics Weekly|language=en}}</ref>

"There is a lot of investment that needs to go on in the equipment community to make that happen. And the value at the end of the day – so that customers would buy that equipment – I think is dubious."<ref>{{cite web|url=http://www.electronicsweekly.com/mannerisms/manufacturing/6706-2014-02/|title=450mm May Never Happen, says Micron CEO|date=11 February 2014|website=electronicsweekly.com}}</ref> As of March 2014, Intel Corporation expected 450&nbsp;mm deployment by 2020 (by the end of this decade).<ref name="intel450mm">{{cite web | url = http://blog.timesunion.com/business/intel-says-450mm-will-deploy-later-in-decade/59430/ | title = Intel says 450&nbsp;mm will deploy later in decade |date=2014-03-18 | access-date = 2014-05-31}}</ref> Mark LaPedus of semiengineering.com reported in mid-2014 that chipmakers had delayed adoption of 450&nbsp;mm "for the foreseeable future." According to this report some observers expected 2018 to 2020, while G. Dan Hutcheson, chief executive of VLSI Research, didn't see 450mm fabs moving into production until 2020 to 2025.<ref>{{cite news |last=LaPedus |first=Mark |url=http://semiengineering.com/is-450mm-dead-in-the-water/ |title=Is 450mm Dead In The Water? |work=semiengineering.com |location=California |publisher=Sperling Media Group LLC |date=2014-05-15  |archive-url=https://web.archive.org/web/20140605134348/http://semiengineering.com/is-450mm-dead-in-the-water/ |archive-date=2014-06-05 |access-date=2014-06-04 |quote=Intel and the rest of the industry have delayed the shift to 450&nbsp;mm fabs for the foreseeable future, leaving many to ponder the following question—Is 450&nbsp;mm technology dead in the water? The answer: 450&nbsp;mm is currently treading water. }}</ref>

The step up to 300&nbsp;mm required major changes, with [[automatic factory|fully automated factories]] using 300&nbsp;mm wafers versus barely automated factories for the 200&nbsp;mm wafers, partly because a [[FOUP]] for 300&nbsp;mm wafers weighs about 7.5 kilograms<ref>{{cite web|url=https://www.shinpoly.co.jp/english/product/semiconductor/seimitsu/300gt.html|title=MW 300GT &#124; Wafer Cases &#124; Shin-Etsu Polymer Co., Ltd|website=www.shinpoly.co.jp}}</ref> when loaded with 25 300&nbsp;mm wafers where a [[SMIF (interface)|SMIF]] weighs about 4.8 kilograms<ref>{{cite web|url=http://www.ckplas.com/nen/wafer_smif_pod_8.htm|title=SMIF Pod-Chung King Enterprise Co., Ltd.|website=www.ckplas.com}}</ref><ref>{{cite web|url=http://www.ckplas.com/nen/ppcst_8_open.htm|title=Wafer Cassette-Chung King Enterprise Co., Ltd.|website=www.ckplas.com}}</ref><ref name="auto" /> when loaded with 25 200&nbsp;mm wafers, thus requiring twice the amount of physical strength from factory workers, and increasing fatigue. 300mm FOUPs have handles so that they can be still be moved by hand. 450mm FOUPs weigh 45 kilograms<ref>{{cite web|url=http://450mm.com/blog/2013/04/07/standing-out-from-the-crowd/|title=Standing out from the Crowd on 450mm &#124; 450mm News and Analysis|access-date=2019-05-27|archive-date=2019-05-27|archive-url=https://web.archive.org/web/20190527012152/http://450mm.com/blog/2013/04/07/standing-out-from-the-crowd/}}</ref> when loaded with 25 450&nbsp;mm wafers, thus cranes are necessary to manually handle the FOUPs<ref>{{cite web|url=http://www.h-square.com/O_Ergolifts.html|title=H-Square Ergolift Cleanroom Lift Carts|website=www.h-square.com|access-date=2019-05-27|archive-url=https://web.archive.org/web/20190527012153/http://www.h-square.com/O_Ergolifts.html|archive-date=2019-05-27}}</ref> and handles are no longer present in the FOUP. FOUPs are moved around using material handling systems from [[Muratec]] or [[Daifuku (company)|Daifuku]]. These major investments were undertaken in the [[economic downturn]] following the [[dot-com bubble]], resulting in huge resistance to upgrading to 450&nbsp;mm by the original timeframe. On the ramp-up to 450&nbsp;mm, the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2–4 times longer to cool, and the process time will be double.{{cn|date=December 2024}} All told, the development of 450&nbsp;mm wafers requires significant engineering, time, and cost to overcome.

== Analytical die count estimation ==
In order to minimize the cost per [[die (integrated circuit)|die]], manufacturers wish to maximize the number of dies that can be made from a single wafer; dies always have a square or rectangular shape due to the constraint of [[wafer dicing]]. In general, this is a [[Computational complexity theory|computationally complex]] problem with no analytical solution, dependent on both the area of the dies as well as their [[aspect ratio]] (square or rectangular) and other considerations such as the width of the [[Die preparation#Semiconductor-die cutting|scribeline]] or saw lane, and additional space occupied by alignment and [[Wafer testing|test structures]]. (By simplifying the problem so that the scribeline and saw lane are both zero-width, the wafer is perfectly circular with no flats, and the dies have a square aspect ratio, we arrive at the [[Gauss circle problem|Gauss Circle Problem]], an unsolved open problem in mathematics.)

Note that formulas estimating the gross dies per wafer ('''DPW''') account only for the number of complete dies that can fit on the wafer; gross DPW calculations do ''not'' account for yield loss among those complete dies due to defects or parametric issues.{{Citation needed|date=February 2021}}

[[File:Wafermap showing fully and partially patterned dies.svg|thumb|Wafermap showing fully patterned dies, and partially patterned dies which don't fully lie within the wafer]]

Nevertheless, the number of gross DPW can be estimated starting with the [[first-order approximation]] or [[floor function]] of wafer-to-die area ratio,
:<math>DPW = \left\lfloor\frac{\pi r^2}{S}\right\rfloor = \left\lfloor\frac{\pi d^2}{4S}\right\rfloor</math>,
where
* <math>d</math> is the wafer diameter (typically in mm)
* <math>S</math> the size of each die (mm<sup>2</sup>) including the width of the scribeline ( or in the case of a saw lane, the [[kerf]] plus a tolerance).

This formula simply states that the number of dies which can fit on the wafer [[pigeonhole principle|cannot exceed]] the area of the wafer divided by the area of each individual die. It will always overestimate the true best-case gross DPW, since it includes the area of partially patterned dies which do not fully lie on the wafer surface (see figure). These partially patterned dies don't represent complete [[integrated circuit|IC]]s, so they usually cannot be sold as functional parts.{{Citation needed|date=February 2021}}

Refinements of this simple formula typically add an edge correction, to account for partial dies on the edge, which in general will be more significant when the area of the die is large compared to the total area of the wafer. In the other limiting case (infinitesimally small dies or infinitely large wafers), the edge correction is negligible.{{Citation needed|date=February 2021}}

The correction factor or correction term generally takes one of the forms cited by De Vries:<ref name="devries">{{cite journal|author1=Dirk K. de Vries|year=2005|title=Investigation of gross die per wafer formulas|journal=IEEE Transactions on Semiconductor Manufacturing|volume=18|issue=February 2005|pages=136–139|doi=10.1109/TSM.2004.836656|s2cid=32016975}}</ref>

:<math>DPW = \frac{\displaystyle \pi d^2}{4S} - \frac{\displaystyle \pi d}{\sqrt{2S}}</math> (area ratio – circumference/(die diagonal length))
:or <math>DPW = \left(\frac{\displaystyle \pi d^2}{4S}\right) \exp(-2 \sqrt{S}/d)</math> (area ratio scaled by an exponential factor)
:or <math>DPW = \frac{\displaystyle \pi d^2}{4S} \left(1 - \frac{\displaystyle 2\sqrt{S}}{d} \right)^2</math> (area ratio scaled by a polynomial factor).

Studies comparing these analytical formulas to [[brute-force search|brute-force]] computational results show that the formulas can be made more accurate, over practical ranges of die sizes and aspect ratios, by adjusting the coefficients of the corrections to values above or below unity, and by replacing the linear die dimension <math>\sqrt{S}</math> with <math>(H+W)/2</math> (average side length) in the case of dies with large aspect ratio:<ref name="devries" />

:<math>DPW = \frac{\displaystyle \pi d^2}{4S} - 0.58^{*} \frac{\displaystyle \pi d}{\sqrt{S}}</math>
:or <math>DPW = \left(\frac{\displaystyle \pi d^2}{4S}\right) \exp(-2.32^{*} \sqrt{S}/d)</math>
:or <math>DPW = \frac{\displaystyle \pi d^2}{4S} \left(1 - \frac{\displaystyle 1.16^{*} \sqrt{S}}{d} \right)^2</math>.

== Compound semiconductors ==

While silicon is the prevalent material for wafers used in the [[electronics industry]], other [[compound semiconductor|compound]] [[List of semiconductor materials|III-V]] or [[List of semiconductor materials|II-VI]] materials have also been employed. [[Gallium arsenide]] (GaAs), a [[III-V semiconductor]] produced via the Czochralski method, [[gallium nitride]] (GaN) and [[silicon carbide]] (SiC) are also common wafer materials, with GaN and [[sapphire]] being extensively used in [[LED]] manufacturing.<ref name=Grover>{{cite book |title=Microelectronic Materials |last=Grovenor |first= C. |year= 1989 |isbn=978-0-85274-270-9 |publisher=CRC Press |pages=113–123 |url=https://books.google.com/books?id=Ecl_mnz1xcUC&q=GaAs+Wafer+Manufacture&pg=PA122 |access-date=2008-02-25}}</ref> 
== See also ==

{{Div col|colwidth=25em}}
* [[Die preparation]]
* [[Epitaxial wafer]]
* [[Epitaxy]]
* [[Monocrystalline silicon]]
* [[Polycrystalline silicon]]
* [[Rapid thermal processing]]
* [[RCA clean]]
* [[SEMI font]]
* [[Silicon on insulator]] (SOI) wafers
* [[Solar cell]]
* [[Solar panel]]
* [[Wafer bonding]]
{{Div col end}}

== References ==

{{Reflist|30em}}

== External links ==

{{Commons category|Wafers}}
* {{usurped|1=[https://archive.today/20160105165200/http://www.f450c.org/infographic/ Evolution of the Silicon Wafer]}} by F450C -An infographic about the history of the silicon wafer.

{{DEFAULTSORT:Wafer (Electronics)}}
[[Category:Semiconductor device fabrication]]