Editing Tape-out

{{Short description|Final stage of the design of electronic circuits before fabrication}}
{{Use American English|date = April 2019}}

In [[electronics design|electronics]] and photonics design, '''tape-out''' or '''tapeout''' is the final stage of the [[integrated circuit design|design process]] for [[integrated circuit]]s or [[printed circuit board]]s before they are sent for manufacturing. The tapeout is specifically the point at which the graphic for the [[photomask]] of the circuit is sent to the fabrication facility. The name originates from the use of magnetic tape to send the data to the manufacturing facility.<ref name=":0">{{Cite web|url=https://www.theregister.co.uk/1999/07/14/what_the_hell/|title=What the Hell is… a tapeout?|last=Magee|first=Mike|date=July 14, 1999|website=[[The Register]]|language=en-GB|access-date=April 2, 2009}}</ref>

== Procedures involved ==
The term ''tapeout'' currently is used to describe the creation of the photomask itself from the final approved electronic CAD file. Designers may use this term to refer to the writing of the final file to disk or CD and its subsequent transmission to the [[semiconductor foundry]]; however, in current practice, the foundry will perform checks and make modifications to the mask design specific to the manufacturing process before actual tapeout. These modifications of the [[Mask data preparation|mask data]] include:<ref name="Layout_book">{{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|pages=102–110|chapter=Chap. 3.3: Mask Data: Layout Post Processing|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0|isbn=978-3-030-39284-0|s2cid=215840278 }}</ref> 
* ''Chip finishing'' which includes custom designations and structures to improve [[design for manufacturability (IC)|manufacturability]] of the layout. Examples of the latter are a seal ring and filler structures.
* Producing a ''reticle layout'' with test patterns and alignment marks.<ref name="Layout_book" /> 
* ''Layout-to-mask preparation'' that enhances layout data with graphics operations and adjusts the data to mask production devices. This step includes [[resolution enhancement technologies]] (RET), such as [[optical proximity correction]] (OPC) which corrects for the wave-like behavior of light when etching the nano scale features of the most modern integrated circuits.<ref name=":0" />

A modern [[integrated circuit]] has to go through a long and complex design process before it is ready for tape-out. Many of the steps along the way use software tools collectively known as [[electronic design automation]] (EDA).  The design must then go through a series of verification steps collectively known as "[[signoff (electronic design automation)|signoff]]" before it can be taped-out. Tape-out is usually a cause for celebration by everyone who worked on the project, followed by trepidation awaiting the [[prototype|first article]], the first physical samples of a chip from the manufacturing facility ([[semiconductor foundry]]).

First tapeout is rarely the end of work for the design team. Most chips will go through a series of iterations, called "spins", in which errors are detected and fixed after testing the first article. Many different factors can cause a spin, including:
*The taped-out design fails final checks at the foundry due to problems manufacturing the design itself.
*The design is successfully fabricated, but the first article fails functionality tests.

== Naming == 
The roots of the term can be traced back to the time when paper tape and later magnetic tape reels were loaded with the final electronic files used to create the [[photomask]] at the factory.<ref name=":0" /><ref>{{cite web |last1=Schaffer |first1=Toby |title=An Introduction to IC Design Under Linux |url=https://www.linuxjournal.com/article/1317 |website=Linux Journal |access-date=15 October 2023}}</ref><ref>{{cite book |last1=Xiu |first1=Liming |title=VLSI Circuit Design Methodology Demystified |date=2008 |publisher=IEEE Press |isbn=978-0-470-12742-1 |page=184}}</ref>

A synonym used at [[IBM]] is ''RIT'' (release interface tape). IBM differentiates between ''RIT-A'' for the non-metallic structures and ''RIT-B'' for the metal layers.<ref>{{cite patent|country=US|number=8166439|title=Techniques for Selecting Spares to Implement a Design Change in an Integrated Circuit|gdate=2012-4-24}}</ref>
A synonym used at [[Texas Instruments]] is PG (pattern generation).{{cn|date=July 2024}}

==See also==
* [[Mask data preparation]]
* [[Semiconductor fabrication]]
* [[GDSII]]

==References==
{{Reflist}}

{{DEFAULTSORT:Tape-Out}}
[[Category:Electronic design]]