Editing SuperH

{{Short description|Instruction set architecture by Hitachi}}
{{Infobox CPU architecture
| name       = SuperH (SH)
| designer   = [[Hitachi]]
| bits       = 32-bit (32 → 64)
| introduced = 1992<ref>{{cite web |title=The Story of the Hitachi SH-2 and the Sega Saturn |url=https://www.sega-16.com/forum/showthread.php?33527-The-Story-of-the-Hitachi-SH-2-and-the-Sega-Saturn |website=www.sega-16.com |publisher=Renesas |access-date=27 February 2023 | archive-url = https://web.archive.org/web/20230227165625/https://www.sega-16.com/forum/showthread.php?33527-The-Story-of-the-Hitachi-SH-2-and-the-Sega-Saturn | archive-date=2023-02-27}}</ref>
| version    =
| design     = RISC
| type       =
| encoding   = SH-2: 16-bit instructions<br />SH-2A and newer: mixed 16- and 32-bit instructions
| page size  = 
| branching  =
| endianness = Bi
| extensions =
| open       = Yes, and royalty-free<ref>[http://j-core.org J-core Open Processor]</ref>
| registers  =
}}
'''SuperH''' (or '''SH''') is a [[32-bit]] [[reduced instruction set computing]] (RISC) [[instruction set architecture]] (ISA) developed by [[Hitachi]] and currently produced by [[Renesas]]. It is implemented by [[microcontroller]]s and [[microprocessor]]s for [[embedded system]]s.

At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the [[processor register|register file]] was smaller and instructions were generally two-operand format. However for the market the SuperH was aimed at, this was a small price to pay for the improved memory and [[processor cache]] efficiency.

Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the [[machine code]] to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a [[compressed instruction set]] and is also used by other companies, the most notable example being [[ARM architecture|ARM]] for its [[ARM architecture#Thumb|Thumb]] instruction set.

In 2015, many of the original [[patent]]s for the SuperH architecture expired and the SH-2 CPU was reimplemented as [[open source hardware]] under the name [[#J Core|J2]].

==History==
===SH-1 and SH-2===
[[Image:HD6417095 01.jpg|150px|thumb|SH-2 on Sega 32X and Sega Saturn]]
The SuperH processor core family was first developed by [[Hitachi]] in the early 1990s. The design concept was for a single [[instruction set]] (ISA) that would be [[upward compatible]] across a series of [[CPU core]]s.

In the past, this sort of design problem would have been solved using [[microcode]], with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models.

One of the key realizations during the development of the [[RISC]] concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported {{code|MUL}}, {{code|DMULS}} and {{code|DMULU}}, whereas the SH-1 would cause a trap if these were encountered.{{sfn|Program|1996|p=1}}

The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions.{{sfn|Program|1996|p=1}} The SH-1 and the SH-2 were used in the [[Sega Saturn]], [[Sega 32X]] and [[Capcom CPS-3]].<ref>{{cite web |title=CP System III (CPS3) Hardware (Capcom) |url=https://www.system16.com/hardware.php?id=799 |website=www.system16.com |publisher=System 16 |access-date=3 August 2019}}</ref>

The ISA uses [[16-bit]] instructions for better code density than 32-bit instructions, which was important at the time due to the high cost of [[DRAM|main memory]] and the implementation cost of cache. As of 2023, code density is still important for small embedded systems and massively multicore processors. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the original SuperH ISA, there were only 16 general registers, requiring four bits for the source and another four for the destination; however some instructions have an implied R0, R15, or a system register as an extra operand. The instruction opcode is four, eight, twelve, or sixteen bits long, and the remaining four-bit fields are used for register or immediate operands in various ways: there are twelve classes of instructions, for a total of 142 instructions in SH-2.{{sfn|Program|1996|pp=30-33}}

Delayed branches are introduced for both SH-1 and SH-2. Unconditional branch instructions have one [[delay slot]].<ref>{{cite web |url=https://www.renesas.com/us/en/document/mah/superh-risc-engine-sh7020-and-sh7021-hd6437020-hd6477021-hd6437021-hd6417021?r=469371 |page=19,48 |title=SH7020 and SH7021 Hardware ManualSuperH™ RISC engine |accessdate=2023-12-02}}</ref>

===SH-3===
A few years later, the SH-3 core was added to the family; new features included another [[interrupt]] concept, a [[memory management unit]] (MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68.{{sfn|Program|1996|p=1}} The SH-3 was [[Endianness#Bi-endian hardware|bi-endian]], running in either big-endian or little-endian byte ordering.

The SH-3 core also added a [[digital signal processing|DSP]] extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated [[Multiply–accumulate|MAC]]-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core.

Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.<ref>{{cite web |url=http://segatech.com/technical/cpu/tech_sh4.html |archive-url=https://web.archive.org/web/20160305103423/http://segatech.com/technical/cpu/tech_sh4.html |archive-date=5 March 2016 |title=360-MIPS SuperH RISC Processor Enables Personal Access Systems SH7750 Launches the SH-4 Series |date = November 1997 }}</ref>

===SH-4===
In 1997, Hitachi and [[STMicroelectronics]] (STM) started collaborating on the design of the SH-4 for the [[Dreamcast]]. SH-4 featured [[superscalar]] (2-way) instruction execution and a [[vector processor|vector]] [[floating-point unit]] (particularly suited to [[3D graphics]]). Standard chips based on the SH-4 were introduced around 1998.<ref name=sh5/>

===Licensing===
In early 2001, Hitachi and STM formed the [[patent holding company|IP company]] SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of Hitachi.<ref name=sh5>{{cite web |title=STMicro, Hitachi plan new company to develop RISC cores|url=http://www.eetimes.com/document.asp?doc_id=1180485 |date=3 April 2001 |website=EE Times|quote=Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. They jointly developed the 32-bit SH4 RISC processor core, and began development of the SH5 architecture, which will now be completed by SuperH. SuperH's initial product will be the SH4 core. Earlier SH versions will not be part of the spin-off agreement.}}</ref><ref>{{cite web|title=SuperH, Inc. formed by Hitachi and STMicroelectronics to Boost the Proliferation of SuperH Cores in Embedded Microprocessor Applications|url=http://investors.st.com/phoenix.zhtml?c=111941&p=irol-newsArticle_print&ID=1454682|archive-url=https://archive.today/20160219085937/http://investors.st.com/phoenix.zhtml?c=111941&p=irol-newsArticle_print&ID=1454682|url-status=dead|archive-date=February 19, 2016}}</ref>

In 2003, Hitachi and [[Mitsubishi Electric]] formed a joint-venture called [[Renesas Electronics|Renesas Technology]], with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores.<ref>{{cite web|url=https://www.eetimes.com/renesas-to-take-over-superh-core-business/|date=28 September 2004|website=EE Times|title=Renesas to take over SuperH core business |first=Peter |last=Clarke}}</ref> Renesas Technology later became Renesas Electronics, following their merger with [[NEC Electronics]].

The SH-5 design supported two modes of operation: SHcompact mode, which is equivalent to the user-mode instructions of the SH-4 instruction set; and SHmedia mode, which is very different in that it uses 32-bit instructions with sixty-four 64-bit integer registers and [[Single instruction, multiple data|SIMD]] instructions. In SHmedia mode the destination of a [[branch (computer science)|branch]] (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; [[ARM architecture|ARM]] processors have a 16-bit [[ARM architecture#Thumb|Thumb]] mode (ARM licensed several patents from SuperH for Thumb<ref name="lwn"/>) and [[MIPS architecture|MIPS]] processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.

The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for [[symmetric multiprocessing]].

===Continued availability===
Since 2010, the SuperH CPU cores, architecture and products are with [[Renesas Electronics]] and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms. The system-on-chip products based on SH-3, SH-4 and SH-4A microprocessors were subsequently replaced by newer generations based on licensed CPU cores from [[Arm Ltd.]], with many of the existing models still marketed and sold until March 2025 through the Renesas Product Longevity Program.<ref>{{cite web|url=https://www.renesas.com/us/en/products/microcontrollers-microprocessors/other-mcus-mpus/superh-risc-engine-family-mcus|website=Renesas Electronics|title="SuperH RISC Engine Family MCUs"}}</ref>

As of 2021, the SH72xx microcontrollers based on the SH-2A continue to be marketed by Renesas with guaranteed availability until February 2029, along with newer products based on several other architectures including [[Arm architecture|Arm]], [[RX microcontroller family|RX]], and [[V850|RH850]].

===J Core===
{{Distinguish|Samsung Galaxy J2 Core}}
The last of the SH-2 patents expired in 2014. At [[LinuxCon]] Japan 2015, j-core developers presented a [[clean room design|cleanroom reimplemention]] of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired [[trademarks]]).<ref name="lwn">{{cite web|url=http://lwn.net/Articles/647636|title=Resurrecting the SuperH architecture|author=Nathan Willis|date=June 10, 2015|publisher=[[LWN.net]]}}</ref><ref name="0pf_jcore">{{cite web|url=http://j-core.org|title=J Cores|publisher=j-core|access-date=April 27, 2016|url-status=dead|archive-url=https://web.archive.org/web/20160511092659/http://j-core.org/|archive-date=May 11, 2016}}</ref> Subsequently, a design walkthrough was presented at ELC 2016.<ref>{{cite web |url=http://j-core.org/talks/ELC-2016.pdf |archive-url=https://web.archive.org/web/20160617085346/http://j-core.org/talks/ELC-2016.pdf |archive-date=2016-06-17 |url-status=live |title=j-core Design Walkthrough}}</ref>

The [[open-source license|open source]] [[Berkeley Software Distribution|BSD]]-licensed [[VHDL]] code for the J2 core has been proven on [[Xilinx]] [[FPGA]]s and on [[ASIC]]s manufactured on [[TSMC]]'s [[180 nm]] process, and is capable of booting [[μClinux]].<ref name="lwn"/>  J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine-generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA.  Additional instructions are easy to add.  J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support.  Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire<!--expired?--> in 2016–2017.<ref name="lwn"/>{{needs update|date=June 2022}}

Several features of SuperH have been cited as motivations for designing new cores based on this architecture:<ref name="lwn"/>

* High [[code density]] compared to other 32-bit [[RISC]] [[instruction set architecture|ISA]]s such as [[ARM architecture|ARM]] or [[MIPS architecture|MIPS]]<ref name="weaver2015">{{cite news|author=V.M. Weaver|title=Exploring the Limits of Code Density (Tech Report with Newest Results)|date=17 March 2015|url=http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf |archive-url=https://web.archive.org/web/20150713143728/http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf |archive-date=2015-07-13 |url-status=live}}</ref> important for cache and memory bandwidth performance
* Existing [[C compiler|compiler]] and [[operating system]] support ([[Linux]], [[Windows Embedded]], [[QNX]]<ref name="0pf_jcore"/>)
* Extremely low ASIC [[semiconductor fabrication|fabrication]] costs now that the patents are expiring (around {{USD|0.03}} for a dual-core J2 core on TSMC's 180&nbsp;nm process).
* Patent- and royalty-free (BSD-licensed) implementation
* Full and vibrant community support
* Availability of low cost hardware development platform for zero cost FPGA tools
* CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation
* Clean, modern design with open source design, generation, simulation and verification environment

==Models==
{|class="wikitable" style="float:right; text-align:right"
|-
|+ Generation comparison<ref name="FumioArakawa">{{Cite web |url=https://old.hotchips.org/wp-content/uploads/hc_archives/hc13/2_Mon/05hitachi.pdf |title=SH-5: A First 64-bit SuperH Core with Multimedia Extension |author=Fumio Arakawa |publisher=Hitachi, Ltd. |format=PDF; 617 kB |date=2013-07-27 |access-date=2022-02-08}}</ref>
! rowspan="2" | !! rowspan="2" | Clock<br />[MHz] !! colspan="3" | [[Computer performance]] !! rowspan="2" | Image
|-
! [[Million instructions per second|MIPS]] !! MOPS !! [[GFLOPS]]
|-
! SH-1
| 20 || 20 || || || [[File:Casio-Loopy-Motherboard-FL (cropped) SuperH HD6437021.jpg|130px|alt=SH-1-Prozessor]]
|-
! SH-2
| 28,7 || 78 || 120 || || [[File:HD6417095 01.jpg|130px|alt=SH-2-Prozessor]]
|-
! SH-3
| 200 || 260 || 400 || || [[File:HD6417709A 02.jpg|130px|alt=SH-3-Prozessor]]
|-
! SH-4
| 200 || 480 || || 1,9 || [[File:SH7091 01.jpg|130px|alt=SH-4-Prozessor]]
|-
! SH-5
| 400 || 700 || 9600 || 2,8 || 
|-
! ''SH-6''
| || >2000 || >24000 || >7,0 ||
|}

The family of SuperH CPU cores includes:
* SH-1 – used in microcontrollers for deeply embedded applications ([[CD-ROM]] drives, [[major appliance]]s, etc.)
* SH-2 – used in microcontrollers with higher performance requirements, networking applications, and also in video game consoles, like the [[Sega Saturn]] and [[Sega 32X]] add-on. The SH-2 has also found home in many automotive [[engine control unit]] applications, including [[Subaru]], [[Mitsubishi Motors|Mitsubishi]], and [[Mazda]].
* SH-2A – The SH-2A core is an extension of the SH-2 core including a few extra instructions but most importantly moving to a superscalar architecture (it is capable of executing more than one instruction in a single cycle) and two five-stage pipelines. It also incorporates 15 register banks to facilitate an interrupt latency of 6 clock cycles. It is also strong in motor control application but also in multimedia, car audio, powertrain, automotive body control and office + building automation
* SH-DSP – initially developed for the [[mobile phone]] market, used later in many consumer applications requiring DSP performance for [[JPEG]] compression etc.
* SH-3 – used for mobile and handheld applications such as the [[Jornada (PDA)|Jornada]], strong in [[Windows CE]] applications and market for many years in the car navigation market. The [[Arcade system board#Cave|Cave CV1000]], similar to the [[Sega NAOMI]] hardware's CPU, also made use of this CPU. The Korg Electribe EMX and ESX music production units also use the SH-3.<ref>{{Cite web |last=Kuwabara |first=M. |date=25 July 2019 |title=Korg EMX / ESX Service Manual |url=http://dealers.korgusa.com/svcfiles/ESX1_Svc_%20man.pdf |archive-url=https://web.archive.org/web/20190713235231/http://dealers.korgusa.com/svcfiles/ESX1_Svc_%20man.pdf |archive-date=13 July 2019}}</ref>
* SH-3-DSP – used mainly in multimedia terminals and networking applications, also in printers and fax machines
* SH-4 – used whenever high performance is required such as car multimedia terminals, [[video game console]]s, most notably the [[Dreamcast]], or [[set-top box]]es
* SH-5 – used in high-end 64-bit multimedia applications
* SH-X – mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones
* SH-Mobile – SuperH Mobile Application Processor; designed to offload application processing from the baseband LSI

===SH-2===
[[File:Denso-SH2.jpg|thumb|upright|Hitachi SH-2 CPU]]

The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware [[multiply–accumulate]] (MAC) block for DSP algorithms and has a five-stage pipeline.

The SH-2 has a cache on all [[Read-only memory|ROM]]-less devices.

It provides 16 general-purpose registers, a vector-base register, global-base register, and a procedure register.

Today the SH-2 family stretches from 32&nbsp;KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.

===SH-2A===
The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006.

New features on the SH-2A core include:
* Superscalar architecture: execution of 2 instructions simultaneously
* [[Harvard architecture]]
* Two 5-stage pipelines
* Mixed 16-bit and 32-bit instructions
* 15 register banks for interrupt response in 6&nbsp;cycles.
* Optional FPU

The SH-2A family today spans a wide memory field from 16&nbsp;KB up to and includes many ROM-less variations. The devices feature standard peripherals such as [[Controller-area network|CAN]], [[Ethernet]], [[USB]] and more as well as more application-specific peripherals such as [[Motor controller|motor control]] timers, [[Thin-film transistor|TFT]] controllers and peripherals dedicated to automotive powertrain applications.
===SH-3===
[[File:Hitachi SH3.jpg|thumb|upright|Hitachi SH-3 CPU ([[Ball grid array|BGA]] version)]]

===SH-4===
The SH-4 is a RISC CPU and was developed for primary use in multimedia applications, such as Sega's [[Dreamcast]] and [[List of Sega arcade system boards#Sega Naomi|NAOMI]] game systems. It includes a much more powerful floating-point unit{{ref|casio|[note]}} and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.

SH-4 features include:
* FPU with four floating-point multipliers, supporting 32-bit single-precision and 64-bit double-precision floats
* 4D floating-point [[dot-product operation]] and [[matrix–vector multiplication]]
* 128-bit floating-point bus allowing 3.2&nbsp;GB/sec transfer rate from the data cache
* 64-bit external data bus with 32-bit memory addressing, allowing a maximum of 4&nbsp;GB addressable memory (see [[Byte addressing]]) with a transfer rate of 800&nbsp;MB/sec
* Built-in interrupt, DMA, and power management controllers

{{note|casio}}There is no FPU in the custom SH-4 made for Casio, the SH7305.

===SH-5===
The SH-5 is a 64-bit RISC CPU.<ref>{{cite web|title=SH-5 CPU Core, Volume1: Architecture|url=http://lars.nocrew.org/computers/processors/SuperH/cpush5v1.pdf |archive-url=https://web.archive.org/web/20090320050543/http://lars.nocrew.org/computers/processors/SuperH/cpush5v1.pdf |archive-date=2009-03-20 |url-status=live}}</ref>

Almost no non-simulated SH-5 hardware was ever released,<ref>{{cite web |title=Wasabi SH-5 Press Release|url=http://www.bsdnewsletter.com/2002/10/News47.html|date=8 March 2016}}</ref> and, unlike the still-live SH-4, support for SH-5 was dropped from [[GNU Compiler Collection|GCC]]<ref>{{cite web |title=GCC 7 Release Series Changes, New Features, and Fixes|url=https://gcc.gnu.org/gcc-7/changes.html|date=2 February 2018}}</ref> and Linux.

===SH-6===
SH-6 was an announced but never implemented further development. It was supposed to achieve over 2 GIPS, over 7 GFLOPS and over 24 GOPS.<ref name="FumioArakawa" />

==References==
===Citations===
{{Reflist}}

===Bibliography===
* {{cite book |url=https://antime.kapsi.fi/sega/files/h12p0.pdf |title=SuperH RISC Engine SH-1/SH-2 Programming Manual |publisher=Hitachi Americal Ltd. |date=3 September 1996 |access-date=2020-12-06 |ref=CITEREFProgram1996}}
* {{cite book |url=http://www.st.com/st-web-ui/static/active/en/resource/technical/document/user_manual/CD00147165.pdf |title=SH-4 CPU Core Architecture |date=12 September 2002 |publisher=STMicroelectronics and Hitachi Ltd. |id=ADCS 7182230F |access-date=2020-12-06}}

==External links==
* [https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/superh.html Renesas SuperH], Products, Tools, Manuals, App.Notes, Information
* [http://j-core.org J-core Open Processor]
* {{Github|j-core}}
* [https://lore.kernel.org/linux-sh/ Linux SuperH development list]
* {{webarchive |url=https://web.archive.org/web/20160810170747/http://segatech.com/technical/cpu/index.html |date=August 10, 2016 |title=DCTP - Hitachi 200&nbsp;MHz SH-4}}
* [http://wiki.debian.org/SH4 in-progress Debian port for SH4]
* {{cite web |title=The SuperH-3, part 1: Introduction |url=https://devblogs.microsoft.com/oldnewthing/20190805-00/?p=102749 |first=Raymond |last=Chen |work=The Old New Thing |type=blog |date=5 August 2019 |access-date=2024-01-22}}  A 15-part series on programming for the microprocessor.

{{Renesas Electronics}}
{{Hitachi}}
{{RISC-based processor architectures}}
{{CPU technologies}}
{{Multimedia extensions}}

{{DEFAULTSORT:Superh}}
[[Category:SuperH architecture]]
[[Category:Embedded microprocessors]]
[[Category:Instruction set architectures]]
[[Category:Japanese inventions]]
[[Category:Renesas microcontrollers]]
[[Category:Open-source hardware]]
[[Category:32-bit microprocessors]]
[[Category:Open microprocessors]]