Editing NS32000

{{Short description|32-bit microprocessor}}
{{More citations needed|date=February 2015}}

The '''NS32000''', sometimes known as the '''32k''', is a series of [[microprocessor]]s produced by [[National Semiconductor]]. Design work began around 1980 and it was announced at the [[International Solid-State Circuits Conference]] in April 1981.

The first member of the family came to market in 1982, briefly known as the '''16032''' before being renamed as the '''32016'''.<ref name="series_32000_software_catalog">{{ cite book | url=https://archive.org/details/bitsavers_nationalda000SoftwareCatalog_4036232/page/n4/mode/1up | title=Series 32000 Software Catalog | publisher=National Semiconductor Corporation | date=1984 | access-date=8 November 2021 | quote=We have recently renamed our 32-bit microprocessor products from the NS16000 family to Series 32000. This program was effective immediately following the signing of Texas Instruments, Inc. as our second source for the Series 32000.}}</ref> It was the first general-purpose microprocessor on the market that used [[32-bit]] data internally: the [[Motorola 68000]] had 32-bit registers and instructions to perform 32-bit arithmetic, but used a 16-bit [[arithmetic logic unit|ALU]] for arithmetic operations on data, and thus took twice as long as the 32016 to perform those arithmetic operations.<ref name="Starnes">{{cite magazine |last=Starnes |first=Thomas W. |date=April 1983 |url=http://www.easy68k.com/paulrsm/doc/dpbm68k1.htm |title=Design Philosophy Behind Motorola's MC68000 |magazine=[[Byte (magazine)|Byte]] |volume=8 |issue=4 |access-date=2018-06-19}}</ref><ref name="leedy198304"/> However, the 32016 contained many bugs and often could not be run at its rated speed. These problems, and the presence of the otherwise similar 68000 which had been available since 1980, led to little use in the market despite considerable early interest.

Several improved versions followed, including 1985's '''32032''' which was essentially a bug-fixed 32016 with an external 32-bit data bus. While it offered about 50% better speed than the 32016, it was outperformed by the 32-bit [[Motorola 68020]], released a year prior. The '''32532''', released in 1987, outperformed the contemporary [[Motorola 68030]] by almost two times, but by this time most interest in microprocessors had turned to [[RISC]] platforms and this otherwise excellent design saw almost no use as well.

National was working on further improvements in the '''32732''', but eventually gave up attempting to compete in the [[central processing unit]] (CPU) space. Instead, the basic 32000 architecture was combined with several support systems and relaunched as the '''Swordfish''' [[microcontroller]]. This had some success in the market before it was replaced by the [[CompactRISC]] architecture in mid-1990s.

==Design concept==
[[File:Kl National Semiconductor NS32008.jpg|thumb|NS32008 microprocessor]]

The NS32000 series traces its history to an effort by National Semiconductor to produce a single-chip implementation of the [[VAX-11]] architecture.<ref name="tilson198310">{{cite magazine | url=https://archive.org/stream/byte-magazine-1983-10/1983_10_BYTE_08-10_UNIX#page/n267/mode/2up | title=Moving Unix to New Machines | magazine=BYTE | volume=8 | issue=10 | date=October 1983 | access-date=31 January 2015 | author=Tilson, Michael | pages=266–276}}</ref> The VAX is well known for its highly "orthogonal" [[instruction set architecture]] (ISA), in which any instruction can be applied to any data. For instance, an <code>ADD</code> instruction might add the contents of two [[processor register]]s, or one register against a value in memory, two values in memory, or use the register as an offset against an address. This flexibility was considered the paragon of design in the era of [[complex instruction set computer]]s (CISC).<ref name="leedy198304"/>

National took [[Digital Equipment Corporation]] (DEC) to court in [[California]] to ensure the legality of the design, but when DEC had the lawsuit moved to [[Massachusetts]], DEC's home state, the lawsuit was dropped and the Series 32000 architecture was developed instead. Although the new [[instruction set architecture]] was not VAX-11 compatible, it did retain its highly "[[orthogonal instruction set|orthogonal]]" design philosophy. That is, every instruction could be used with any type of data. Articles of the time also referred to this as "symmetrical".<ref name="leedy198304"/>

The original processor family consisted of the NS16032 CPU and a NS16C032 low-power variant, both having a 16-bit data path and so requiring two machine cycles to load a single 32-bit word. Both could be used with the NS16082 [[memory management unit]] (MMU), which provided 24-bit [[virtual memory]] support for up to 16&nbsp;MB physical memory. The NS16008 was a cut-down version with an 8-bit external data path and no virtual memory support, which had a reduced pin count and was thus somewhat easier to implement.<ref name="leedy198304"/> Both the NS16008 and NS16016 were to feature an emulation mode for the [[Intel 8080]] running at four times the speed of that processor.<ref name="interfaceage19811_advances">{{ cite magazine | url=https://archive.org/details/InterfaceAge198111/page/n95/mode/2up | title=Advances in CPU Design | magazine=Interface Age | last1=Cole | first1=Bernard Conrad | date=November 1981 | access-date=2 March 2023 | pages=94–97 }}</ref>

At the same time, National Semiconductor also announced two future versions, the NS32032 and NS32132. The former was essentially a version of the NS16032 with a 32-bit external data bus, allowing it to read data at twice the rate. This was project to be released in 1984. The NS32132 was a version with a 29-bit internal addresses and 32-bit external, allowing it to address a complete 4&nbsp;GB of memory. It was to be released in 1985.<ref name="leedy198304"/>

All of these could also be used with the NS16081 [[floating-point unit]] (FPU).<ref name="leedy198304" />

==Architecture==
{| class="infobox" style="font-size:88%;width:38em;"
|-
|+ NS 32000 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:left;"| <sup>3</sup><sub>1</sub>
| style="width:60px; text-align:center;"| . . .
| style="width:10px; text-align:right;"| <sup>2</sup><sub>3</sub>
| style="width:60px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:60px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:60px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="10" | '''General registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R0
| style="background:white; color:black;"| '''R'''egister 0
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R1
| style="background:white; color:black;"| '''R'''egister 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R2
| style="background:white; color:black;"| '''R'''egister 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R3
| style="background:white; color:black;"| '''R'''egister 3
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R4
| style="background:white; color:black;"| '''R'''egister 4
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R5
| style="background:white; color:black;"| '''R'''egister 5
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R6
| style="background:white; color:black;"| '''R'''egister 6
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| R7
| style="background:white; color:black;"| '''R'''egister 7
|-
|colspan="10" | '''Index registers'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| 0000 0000
| style="text-align:center;padding-right:18%" colspan="7"| SP1
| style="background:white; color:black;"| '''S'''tack '''P'''ointer (user)
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| 0000 0000
| style="text-align:center;padding-right:18%" colspan="7"| SP0
| style="background:white; color:black;"| '''S'''tack '''P'''ointer (interrupt)
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| 0000 0000
| style="text-align:center;padding-right:18%" colspan="7"| SB
| style="background:white; color:black;"| '''S'''tatic '''B'''ase
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| 0000 0000
| style="text-align:center;padding-right:18%" colspan="7"| FP
| style="background:white; color:black;"| '''F'''rame '''P'''ointer
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| 0000 0000
| style="text-align:center;padding-right:18%" colspan="7"| INTBASE
| style="background:white; color:black;"| '''Int'''errupt '''Base'''
|-
|colspan="10" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="2"| 0000 0000
| style="text-align:center;padding-right:18%" colspan="7"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|- style="background:silver;color:black"
| style="background-color:white" colspan="4"| &nbsp;
| style="text-align:left" colspan="5"| MOD
| style="background:white; color:black;"| '''Mod'''ule descriptor
|}
{| style="font-size:88%"
|-
|colspan="18" | '''Program Status Register'''
|-
| style="width:100px; text-align:center"| &nbsp;
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- style="background:silver;color:black"
| style="background-color:white"| &nbsp;
| style="text-align:center"| –
| style="text-align:center"| –
| style="text-align:center"| –
| style="text-align:center"| –
| style="text-align:center"| [[Interrupt flag|I]]
| style="text-align:center"| P
| style="text-align:center"| S
| style="text-align:center"| U
| style="text-align:center"| N
| style="text-align:center"| [[Zero flag|Z]]
| style="text-align:center"| [[Overflow flag|F]]
| style="text-align:center"| –
| style="text-align:center"| –
| style="text-align:center"| L
| style="text-align:center"| T
| style="text-align:center"| [[Carry flag|C]]
| style="background:white; color:black" | '''PSR'''
|}
|}

The processors have 8 general-purpose 32-bit registers, plus a series of special-purpose registers:
* Frame pointer
* Stack pointer (one each for user and supervisor modes)
* Static base register, for referencing global variables
* Link base register for dynamically linked modules (object orientation)
* Program counter
* A typical processor status register, with a low-order user byte and a high-order system byte.
(Additional system registers not listed).

The instruction set is very much in the [[complex instruction set computer|CISC]] model, with 2-operand instructions, memory-to-memory operations, flexible [[addressing mode]]s, and variable-length byte-aligned instruction encoding.  Addressing modes can involve up to two displacements and two memory indirections per operand as well as scaled indexing, making the longest conceivable instruction 23 bytes. The actual number of instructions is much lower than that of contemporary RISC processors.

Unlike some other processors, automatic increment of the base register is not provided; the only exception is a "top of stack" addressing modes that pop sources and push destinations.  Uniquely, the size of the displacement is encoded in its most significant bits: 0, 10 and 11 preceded 7-, 14- and 30-bit signed displacements.  (Although the processors are otherwise consistently little-endian, displacements in the instruction stream are stored in big-endian order).

General-purpose operands are specified using a 5-bit field. To this can be added an index byte (specifying the index register and 5-bit base address), and up to 2 variable-length displacements per operand.

==32016==
The first chip in the series was originally referred to as the 16032, but later renamed 32016 to emphasize its 32-bit internals. This contrasts it with its primary competitor in this space, 1979's Motorola 68000 (68k). The 68k used 32-bit instructions and registers, but its [[arithmetic logic unit]] (ALU), which controls much of the overall processing task, was only 16-bit. This meant it had to cycle 32-bit data through the ALU twice&mdash;in two 16-bit halves&mdash;to complete a 32-bit operation. In contrast, the NS32000 has a 32-bit ALU, so that 32-bit and 16-bit instructions take the same time to complete.

The 32016 first shipped in 1982 in a 48-pin [[dual inline package|DIP]] package. To fit a 32-bit chip into a 48-pin package required the [[data bus]] to be 16-bits wide, and to share pins with the 24-bit [[address bus]]. By sharing pins, external hardware had to latch the address for the memory address while the pins were used in data mode, and this introduces a 1-cycle delay in every access. So while the internal 32-bit implementation improves performance, the small pin-count decreases it again.

It may have been the first 32-bit chip to reach mass production and sale (at least according to National's marketing). In a report in a June 1983 publication, however, it was remarked that National was "promising production quantities this summer" of 16032 parts, having been "shipping sample quantities for several months", with the floating point co-processor sampling "this month".<ref name="pcw198306">{{ cite magazine | url=https://archive.org/details/PersonalComputerWorld1983-06/page/190/mode/1up | title=Super-microprocessors - a status report | last1=Libes | first1=Sol | date=June 1983 | access-date=17 October 2020 | magazine=Personal Computer World | volume=6 | number=6 | pages=190 }}</ref>

Although a 1982 introduction post-dates the 68k by about two years, the 68k was not yet being widely used in the market and the 32016 generated significant interest. Unfortunately, the early versions were filled with bugs and could rarely be run at their rated speed. By 1984, after two years, the errata list still contained items specifying uncontrollable conditions that would result in the processor coming to a halt, forcing a reset.

The original product roadmap envisaged 6&nbsp;MHz and 10&nbsp;MHz parts during 1983 and 12&nbsp;MHz and 14&nbsp;MHz parts during 1984.<ref name="leedy198304">{{cite magazine |url=https://archive.org/details/byte-magazine-1983-04/page/n54/mode/1up |title=The National Semiconductor NS16000 Microprocessor Family |magazine=BYTE |date=April 1983 |access-date=22 August 2020 | volume=8 | issue=4 |last=Leedy |first=Glenn |pages=53–66}}</ref> However, press reports in 1984 indicated difficulties in keeping to this roadmap, with it reportedly having  taken five months to increase the frequency of the parts from 6&nbsp;MHz to 8&nbsp;MHz, and with representatives estimating a further "two, three or five months" to increase the frequency to 10&nbsp;MHz. Two unspecified chips of the five in the chipset were reported to be the cause of these problems.<ref name="acornuser198407">{{cite magazine | url=https://archive.org/details/AcornUser024-Jul84/page/n8/mode/1up | title=Acorn dispels superchip doubt | magazine=Acorn User | issue=24 | date=July 1984 | access-date=28 August 2020 | pages=7}}</ref> An early 1985 article about the 32016-based Whitechapel MG-1 workstation noted that the 32082 memory management unit was "suffering from bugs" and had been situated on its own board providing hardware fixes.<ref name="byte198502">{{ cite magazine
  | url=https://archive.org/details/byte-magazine-1985-02/1985_02_BYTE_10-02_Computing_and_the_Sciences/page/n378/mode/1up
  | title=Realizing a Dream
  | magazine=Byte UK | date=February 1985 | volume=10 | issue=2
  | access-date=18 December 2020
  | last1=Pountain | first1=Dick
  |author-link=Dick Pountain
  | pages=379–382, 384 
}}</ref> In 1986, Texas Instruments announced a "fully qualified 10&nbsp;MHz TI32000 32-bit microprocessor chip set" consisting of the TI32016 CPU and TI32082 memory management unit as 48-pin devices, the TI32201 timing control unit and TI32081 floating-point unit as 24-pin devices, and the TI32202 interrupt control unit as a 40-pin device, with the five-device chipset "priced at $289 in 100-unit quantities".<ref name="computerworld19860616_ti32000">{{ cite magazine | url=https://archive.org/details/computerworld2024unse/page/130/mode/1up | title=Components | magazine=Computerworld | date=16 June 1986 | access-date=9 February 2022 | pages=130 }}</ref>

National changed its design methodology to make it possible to get the part into production and a design system based on the language "Z" was co-developed with the University of Tel-Aviv, close to the "NSC" design centre in [[Herzliya]], Israel. The "Z" language is similar to today's [[Verilog]] and [[VHDL]], but has a Pascal-like syntax and is optimized for [[two-phase clock]] designs. However, by the times the fruit of these efforts were being felt in the design, numerous 68k machines were already on the market, notably the [[Macintosh 128K|Apple Macintosh]], and the 32016 never saw widespread use.

The 32016 has a 16-bit external [[bus (computing)|data bus]], a 24-bit external [[address bus]], and a full 32-bit [[instruction set]]. It also includes a [[coprocessor]] interface, allowing coprocessors such as [[floating-point unit|FPU]]s and [[memory management unit|MMUs]] to be attached as peers to the main processor. The MMU is based on [[demand paging]] virtual memory, which is the most unusual feature compared to the segmented memory approach used by the competition, and has become the standard for how microprocessors are designed today. The architecture supports an instruction restart mechanism on a page fault, which is much cleaner than the Motorola approach to dump the internal status on a page fault, which has to be read back, before the instruction is continued.

[[File:KL National NS32016D.jpg|thumb|NS32016 microprocessor]]
[[File:KL National NS32081.jpg|right|thumb|NS32081 FPU]]

While often compared to the 68k's instruction set, this was rejected by NSC employees; one of the key marketing phrases of the time was "Elegance is Everything", comparing the highly orthogonal Series 32000 to the "kludge". One key difference is Motorola's use of address registers and data registers, with instructions only working on either address or data registers. The Series 32000 has general-purpose registers, described as "address-data" registers in technical documentation.<ref name="ti32000_family_data_manual">{{ cite book | url=https://archive.org/details/bitsavers_tidataBookataManual_13702736/page/n44/mode/1up | title=TI32000 Family Data Manual | publisher=Texas Instruments Incorporated | date=1985 | access-date=8 November 2021 | pages=2–24 | quote=All address-data registers are available to all instructions. Thus, the compiler has freedom in its use of the registers and needn't do much housekeeping. The architecture also enables address-data registers to be used as accumulators, data registers, and address pointers. This represents a great improvement over machines that permit only a few registers to serve as address pointers, creating a bottleneck in address calculations, a very important function in high-level language programming. }}</ref>

==32032==
[[File:KL National NS32032.jpg|right|thumb|NS32032 microprocessor]]

The 32032 was introduced in 1984. It is almost completely compatible with the 32016, but features a 32-bit data bus (although keeping the 24-bit address bus) for somewhat faster performance, described as "minicomputer performance" comparable with that of a VAX-11 system.<ref name="computerworld19840618_rada">{{ cite magazine | url=https://archive.org/details/sim_computerworld_1984-06-18_18_25/page/n34/mode/1up | title=The 32-bit flexible workstation: one supplier's answer for users | magazine=Computerworld | date=18 June 1984 | access-date=10 March 2022 | last1=Rada | first1=Col | pages=35–37, 39–40 }}</ref>{{rp|pages=39|quote=Preliminary benchmark tests indicate that the 32032 delivers minicomputer performance. On computation-intensive programs, the 32032 CPU running with the support of National Semiconductor's 32081 floating-point unit turned in a VAX-11-class performance. }} There was also a 32008, a 32016 with a data bus cut down to 8-bits wide for low-cost applications. It is philosophically similar to the [[Motorola 68008|MC68008]], and equally unpopular.

National also produced a series of related support chips like the NS32081 [[floating point unit]] (FPU), NS32082 [[memory management unit]] (MMU), NS32203 [[direct memory access]] (DMA) and NS32202 [[interrupt controller]]s. With the full set plus memory chips and peripherals, it was feasible to build a 32-bit computer system capable of supporting modern multi-tasking operating systems, something that had previously been possible only on expensive minicomputers and [[mainframe computer|mainframe]]s.

<gallery caption="Die photos" mode="packed">
Image:NS_NS16032_die.JPG|NS16032 CPU
Image:NS_NS16081_die.JPG|NS16081 FPU
Image:NS_NS32032_die.jpg|NS32032 CPU
Image:NS_NS32081_die.JPG|NS32081 FPU
Image:NS_NS32082_die.jpg|NS32082 MMU
Image:NS_NS32202_die.jpg|NS32202 Interrupt controller
Image:NS_NS32203_die.jpg|NS32203 DMA controller
</gallery>

==32332, 32532==
In 1985, National Semi introduced the NS32332, a much-improved version of the 32032.  From the datasheet, the enhancements include "the addition of new dedicated addressing hardware (consisting of a high speed ALU, a [[barrel shifter]] and an address register), a very efficient increased (20 bytes) instruction prefetch queue, a new system/memory bus interface/protocol, increased efficiency slave processor protocol and finally enhancements of microcode."  There was also a new NS32382 MMU, NS32381 FPU and the (very rare) NS32310 interface to a [[Weitek]] FPA. The aggregate performance boost of the NS32332 from these enhancements only made it 50 percent faster than the original NS32032, and therefore less than that of the main competitor, the [[MC68020]].

National Semi introduced the NS32532 in early 1987.  Running at 20-, 25- & 30-MHz, it was a complete redesign of the internal implementation with a five-stage pipeline, an integrated Cache/MMU and improved memory performance, making it about twice as performant as the competing [[MC68030]] and [[i80386]]. At this stage RISC architectures were starting to make inroads, and the main competitors became the now equally dead [[AM29000]] and [[MC88000]], which was considered faster than the NS32532. For floating-point, the NS32532 used the existing NS32381 or the NS32580 interface to a Weitek FPA.<ref>{{cite web|url=http://stuff.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/ns32532.pdf|title=NS32532-20/NS32532-25/NS32532-30 High-Performance 32-Bit Microprocessor|date=1995|publisher=[[National Semiconductor]]}}</ref>  The NS32532 was the basis of the [[PC532]], a "public domain" hardware project, and one of the few to produce a useful machine running a real operating system (in this case, [[Minix]] or [[NetBSD]]).

The semi-mythical NS32732 (sometimes called NS32764), envisioned as the high-performance successor to the NS32532, never came to the market.

==Swordfish==
A derivative of the NS32732 called Swordfish was aimed at [[embedded system]]s and arrived in about 1990. Swordfish has an integrated floating point unit, timers, DMA controllers and other peripherals not normally available in microprocessors. It has a 64-bit data bus and is internally overclocked from 25 to 50&nbsp;MHz. The chief architect of the Swordfish is [[Donald Alpert]], who went on to manage the architectural team designing the [[Pentium]]. The Pentium internal microarchitecture is similar to the preceding Swordfish.

The focus of Swordfish was high-end [[PostScript]] [[laser printer]]s, and performance was exceptional at the time. Competing solutions could render about one new page per minute, but the Swordfish demo unit would print out sixteen pages per minute, limited only by the laser-engine mechanics. On each page it would print out how much time it was idling, waiting for the engine to complete.

The Swordfish die is huge, and it was eventually decided to drop the project altogether, and the product never went into production. The lessons from the Swordfish were used for the CompactRISC designs. In the beginning, there were both a CompactRISC-32 and a CompactRISC-16, designed using "Z". National never brought a chip to the market with the CompactRISC-32 core. National's Research department worked with the University of Michigan to develop the first synthesizable Verilog Model, and Verilog was used from the CR16C and onwards.

==Others==
Versions of the older NS32000 line for low-cost products such as the NS32CG16, NS32CG160, NS32FV16, NS32FX161, NS32FX164 and the NS32AM160/1/3, all based on the NS302CG16 were introduced from 1987 and onwards.

These processors had some success in the [[laser printer]] and [[fax]] market, despite intense competition from [[AMD]] and Intel [[RISC]] chips. Especially the NS32CG16 should be noted. The key difference between this and the NS32C016 is the integration of the expensive timing control unit (TCU) which generates the needed two-phase clock from a crystal, and the removal of the floating point coprocessor support, which freed up microcode space for the useful BitBLT instruction set, which significantly improves the performance in laser printer operations, making this 60,000 transistor chip faster than the 200,000 transistor MC68020. The NS32CG160 is the CG16 with timers and DMA peripherals, while the NS32FV/FX16x chips have extra DSP functionality on top of the CG16 BitBLT core for the fax and [[answering machine]] market. They are complemented by the NS32532 based NS32GX32 later. Unlike the previous chips, there was no extra hardware. The NS32GX32 is the NS32532 without the MMU sold at an attractive price for embedded system. In the beginning, this was just a remarked chip. It is unclear if the chip was redesigned for lower-cost production.

Datasheets exist for an NS32132, apparently designed for multiprocessor systems. This is the NS32032 extended with an arbiter. The bus usage of the NS32032 is about 50 percent, owing to its very compact instruction set, or its very slow pipeline as competitors would phrase it. Indeed, one suggested application of the NS32032 was as part of a "fault-tolerant transaction system" employing "two 32032s in parallel and comparing results on alternate memory cycles to detect soft errors".<ref name="pcw198306" /> The NS32132 chip allows a pair of CPUs to be connected to the same memory system, without much change of the PCB. Prototype systems were built by [[Dataindustrier AB|Diab Data AB]] in [[Sweden]], but did not perform as well as the single-CPU MC68020 system designed by the same company.

<gallery caption="Die photos" mode="packed">
Image:NS_NS32C016_die.jpg|NS32C016 CPU
Image:NS_NS32381_die.JPG|NS32381 FPU
Image:NS_NS32382_die.jpg|NS32382 MMU
Image:NS_NS32532_die.JPG|NS32532 CPU
</gallery>

==Machines using the NS32000 series==
* [[Acorn Cambridge Workstation]] – NS32016 (with 6502-based [[BBC Micro]] host)
* [[BBC Micro expansion unit#32016 Second Processor|BBC Micro 32016 Second Processor]] - a separate expansion for the BBC Micro providing the NS32016 capabilities from the Acorn Cambridge Workstation
* [[Canon Inc.|Canon]] LBP-8 Mark III Laser Printer – NS32CG16
* [[Bill Godbout|CompuPro]] 32016 – NS32016 S-100 Card<ref name="compupro_32016">{{ cite book | url=https://archive.org/details/bitsavers_compuproA2_1562698/mode/2up | title=CPU 32016 Technical Manual | publisher=CompuPro | date=1984 | access-date=9 March 2022 }}</ref>
* Definicon DSI-32 - NS32032 PC Add-On Board<ref name="definicon_dsi-32">{{ cite magazine |last1=Marshall |first1=Trevor |last2=Sccolaro |first2=George |last3=Rand |first3=David|last4=King |first4=Tom |last5=Williams |first5=Vincent | url=https://archive.org/details/BYTE_Vol_10-08_1985-08_The_Amiga | title=The DSI-32 Coprocessor Board, Part I: The Hardware | magazine=BYTE | date=August 1985 | access-date=22 April 2025 | pages=120-136 }}</ref>
* [[Encore Computer|Encore]] Multimax – NS32032, NS32332 and NS32532 Multiprocessor
* [[E-mu Systems]] [[E-mu Emax|Emax]] – NS32008
* E-mu Systems [[E-mu Emulator#Emulator III|Emulator III]] – NS32016
* [[ETH Zurich|ETH Zürich]] [[Ceres (workstation)|Ceres]] workstation – NS32032
* ETH Zürich [[Ceres (workstation)|Ceres-2]] workstation – NS32532
* ETH Zürich [[Ceres (workstation)|Ceres-3]] workstation – NS32GX32
* General Robotics Corp. Python – NS32032 & N32016 [[Q-Bus]] card
* Heurikon VME532 – NS32532 VME Card (with cache)
* [[IBM RT PC]] – Some early models used the NS32081 FPU as a coprocessor for the [[IBM ROMP]] microprocessor
* [[Intermec]] (previously A-Tech and then UBI) Label Printer – NS32CG16
* [[Intergraph]] Interpro 32 (NS 32032)
* Labtam Unix System NS32032 and NS32332 CPUs
* Lauterbach Incircuit Emulator ICE (System Controller 32-bit, first version in 1996, max 16 MB ZIP20-RAM, Z180 to serve Ethernet)
* [[National Semiconductor]] ICM-3216 – NS32016
* National Semiconductor ICM-332-1 – NS32332 w/ NS32016 I/O processor
* National Semiconductor SYS32/20 – NS32016 PC add-on board w/ Unix
* Opus Systems Opus516 Personal Mainframe – NS32016 PC Add-On Board<ref name="byte198504_opus516">{{ cite magazine | url=https://archive.org/details/byte-magazine-1985-04/page/n436/mode/1up | title=IBM PC UNIX Coprocessor | magazine=Byte | date=April 1985 | access-date=24 June 2022 | pages=441 }}</ref>
* Opus Systems Opus532.32 Personal Mainframe – NS32032 PC Add-On Board<ref name="unixreview198602_opus53232">{{ cite magazine | url=https://archive.org/details/sim_unix-review_1986-02_4_2/page/83/mode/1up | title=Opus: UNIX Music To PC Ears | magazine=UNIX Review | date=February 1986 | access-date=24 June 2022 | pages=83 }}</ref>
* [[PC532]] – NS32532
* [[Sequent Computer Systems|Sequent]] Balance – NS32016, NS32032 and NS32332 multiprocessor
* [[Siemens]] PC-MX2 – NS32016
* Siemens MX300-05/-10/-15/-30 – NS32332 (−05/-10) or NS32532 (−15/-30) under [[SINIX]]  (MX300-55 and later use [[Intel 80486|i486]])
* Siemens MX500-75/-85 – NS32532 (2-8x CPUs; Sequent Boards / MX500-90 uses 2-12x i486)
* Symmetric Computer Systems S/375<ref>{{cite web |author=<!-- not stated --> |date=10 Oct 2004 |title=William Jolitz and Symmetric Computer Systems |url=http://jolitz.telemuse.net/william/symmetric |website= |url-status=dead |archive-url=https://web.archive.org/web/20160401034753/https://jolitz.telemuse.net/william/symmetric |archive-date=1 April 2016 |access-date=23 April 2025}}</ref> – NS32016, used to cross-develop [[386BSD]]
* Syte Information Technology Model 300 – NS32032-based Unix graphics workstation,<ref name="computerdesign19840615_32bit">{{ cite magazine | url=https://archive.org/details/bitsavers_ComputerDe23N0719840615_124116179/page/97/mode/1up | title=Thirty-Two Bit Micros Power Workstations | magazine=Computer Design | last1=Mokhoff | first1=Nicolas | date=15 June 1984 | access-date=5 March 2024 | pages=97–100, 102, 104–106, 108–110, 112 }}</ref> several such "multiple tightly coupled microcomputers organized in a mainframe architecture" comprising the Syte Series 3000 "micro-mainframe" running the Global Environment Manager to manage multiple virtual environments on each processor node,<ref name="computerdesign198403_syte">{{ cite magazine | url=https://archive.org/details/bitsavers_computerDe_409597766/page/30/mode/2up | title=Multiple operating systems coexist on multiprocessor system | magazine=Computer Design | date=March 1984 | access-date=5 March 2024 | pages=30, 32 }}</ref> with Syte eventually failing before initial product shipments<ref name="computerdesign198411_syte">{{ cite magazine | url=https://archive.org/details/bitsavers_ComputerDe_161498239/page/8/mode/1up | title=Syte fades from view | magazine=Computer Design | date=November 1984 | access-date=5 March 2024 | pages=8 }}</ref>
* [[Tektronix]] [[Tektronix 4132|4132]]<ref>{{cite web| url=http://bitsavers.trailing-edge.com/pdf/tektronix/catalog/Tektronix_Catalog_1987.pdf |title=TEK PRODUCTS (Catalog) | year=1987 | page=59| publisher=Tektronix |via=[[Bitsavers]] |access-date=22 April 2025}}</ref> workstation - NS32016
* Tektronix [[Tektronix 6100|6100]]<ref>{{cite web| url=http://bitsavers.trailing-edge.com/pdf/tektronix/catalog/Tektronix_Catalog_1985.pdf |title=TEK PRODUCTS (Catalog) | year=1985 | page=49| publisher=Tektronix |via=[[Bitsavers]] |access-date=22 April 2025}}</ref> series - lab controller (6110) and workstations (6120/6130) - NS32016
* Tektronix [[Tektronix 6200|6200]]<ref>{{cite web| url=http://bitsavers.trailing-edge.com/pdf/tektronix/catalog/Tektronix_Catalog_1985.pdf |title=TEK PRODUCTS (Catalog) | year=1985 | page=50| publisher=Tektronix |via=[[Bitsavers]] |access-date=22 April 2025}}</ref> series workstations – NS32016 I/O processor (all models); NS32016 CPU (6205), NS32032 CPU (6210), or multiple NS32032 CPUs (6212)
* [[Tolerant Systems]] Eternity Series  – NS32032 w/ NS32016 I/O processor
* Trinity College Workstation – NS32332
* [[Teklogix]] 9020 network controller – NS32332
* Teklogix 9200 network controller – NS32CG160
* [[Whitechapel Computer Works|Whitechapel]] MG-1 – NS32016
* Whitechapel MG200 – NS32332

== Legacy ==
In June 2015, Udo Möller released a complete [[Verilog]] implementation of an NS32000 processor on [[OpenCores]].<ref>[http://opencores.org/project,m32632 M32632 32-bit Processor] (OpenCores.org)</ref>  Fully software-compatible with an NS32532 CPU with N32381 FPU, it is significantly faster when implemented on an [[Field-programmable gate array|FPGA]],<ref>[http://cpu-ns32k.net/Performance.html M32632 Performance] (cpu-ns32k.net)</ref> both operating at a higher clock rate and using fewer cycles per instruction.

==References==
{{Reflist}}
{{Refbegin}}
* Trevor G. Marshall, George Scolaro and David L. Rand: ''The Definicon DSI-32 Coprocessor''.  [[Micro Cornucopia]], Aug/September 1985,
* Trevor G. Marshall, George Scolaro and David L. Rand: ''The DSI-32 Coprocessor Board''.  Part 1, [[Byte (magazine)|BYTE]], August 1985, pp 120–136; Part 2, BYTE, September 1985, p 116.
{{Refend}}

==External links==

; Datasheets
* [http://www.bitsavers.org/components/national/_dataBooks/1986_National_NS32000_Databook.pdf Data book NS32000 family (1986)]
* [http://stuff.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/ns32532.pdf NS32532]
* [http://stuff.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/ns32c032.pdf NS32C032]
* [http://datasheets.chipdb.org/National/32K/32381/DS009157.PDF NS32381]
* [http://cpu-ns32k.net/Documents.html National Semiconductor's Series 32000 Family], an excellent "fan site" and home of the M32632 FPGA clone.

{{Authority control}}

[[Category:National Semiconductor microprocessors|320xx]]
[[Category:32-bit microprocessors]]