Editing NMOS logic

{{More citations needed|date=January 2024}}
{{short description|Form of digital logic family in integrated circuits}}
'''NMOS''' or '''nMOS''' logic (from N-type metal–oxide–semiconductor) uses [[n-type semiconductor|n-type]] (-) [[MOSFET]]s (metal–oxide–semiconductor [[field-effect transistor]]s) to implement [[logic gate]]s and other [[digital circuit]]s.<ref>{{cite book |author-first1=Mohammed|author-last1=Ferdjallah|chapter=5.4 NMOS and PMOS Logic Gates|title=Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL|chapter-url=https://www.oreilly.com/library/view/introduction-to-digital/9780470900550/chap5-sec004.html|publisher=Wiley|year=2011|via=O'Reilly Media, Inc.|language=en|isbn=9780470900550}}</ref><ref>{{cite journal |last1=Kong |first1=Lingan |last2=Chen |first2=Yang |last3=Liu |first3=Yuan |title=Recent progresses of NMOS and CMOS logic functions based on two-dimensional semiconductors |journal=Nano Research |date=June 2021 |volume=14 |issue=6 |pages=1768–1783 |doi=10.1007/s12274-020-2958-7}}</ref> 

NMOS transistors operate by creating an [[inversion layer (semiconductors)|inversion layer]] in a [[p-type semiconductor|p-type]] transistor body. This inversion layer, called the n-channel, can conduct [[electron]]s between [[n-type semiconductor|n-type]] ''source'' and ''drain'' terminals. The n-channel is created by applying voltage to the third terminal, called the ''gate''. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity saturation.

NMOS AND-by-default logic can produce unusual glitches or buggy behavior in NMOS components, such as the [[6502]] "illegal opcodes" which are absent in CMOS 6502s. In some cases such as Commodore's [[VIC-II]] chip, the bugs present in the chip's logic were extensively exploited by programmers for graphics effects.

For many years, NMOS circuits were much faster than comparable [[PMOS logic|PMOS]] and [[CMOS]] circuits, which had to use much slower p-channel transistors. It was also easier to manufacture NMOS than CMOS, as the latter has to implement p-channel transistors in special n-wells on the p-substrate, not prone to damage from bus conflicts, and not as vulnerable to electrostatic discharge damage. The major drawback with NMOS (and most other [[logic family|logic families]]) is that a [[direct current]] must flow through a logic gate even when the output is in a [[steady state]] (low in the case of NMOS). This means static [[power dissipation]], i.e. power drain even when the circuit is not switching, leading to high power consumption.

Another disadvantage of NMOS circuits is their thermal output. Due to the need to keep constant voltage running through the circuit to hold the transistors' states, NMOS circuits can generate a considerable amount of heat in operation which can reduce the device's reliability. This was especially problematic with the early large gate process nodes in the 1970s. CMOS circuits for contrast generate almost no heat unless the transistor count approaches 1 million.

CMOS components were relatively uncommon in the 1970s-early 1980s and would typically be indicated with a "C" in the part number. Throughout the 1980s, both NMOS and CMOS parts were widely used with CMOS becoming more widespread as the decade went along. NMOS was preferred for components that performed active processing such as CPUs or graphics processors due to its higher speed and cheaper manufacturing cost as these were expensive compared to a passive component such as a memory chip, and some chips such as the [[Motorola 68030]] were hybrids with both NMOS and CMOS sections. CMOS has been near-universal in integrated circuits since the 1990s.

Additionally, just like in [[diode–transistor logic]], [[transistor–transistor logic]], [[emitter-coupled logic]] etc., the asymmetric input logic levels make NMOS and PMOS circuits more susceptible to noise than CMOS. These disadvantages are why [[CMOS logic]] has supplanted most of these types in most high-speed digital circuits such as [[microprocessor]]s despite the fact that CMOS was originally very slow compared to [[logic gate]]s built with [[bipolar transistor]]s.

==Overview==
MOS stands for ''metal-oxide-semiconductor'', reflecting the way MOS-transistors were originally constructed, predominantly before the 1970s, with gates of metal, typically aluminium. Since around 1970, however, most MOS circuits have used [[self-aligned gate]]s made of [[polycrystalline silicon]], a technology first developed by [[Federico Faggin]] at [[Fairchild Semiconductor]]. These [[silicon gate]]s are still used in most types of MOSFET based [[integrated circuit]]s, although metal gates ([[Aluminium|Al]] or [[Copper|Cu]]) started to reappear in the early 2000s for certain types of high speed circuits, such as high performance microprocessors.

The MOSFETs are n-type [[enhancement mode]] transistors, arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage (typically the ground). A [[pull up resistor|pull up]] (i.e. a "load" that can be thought of as a resistor, see below) is placed between the positive supply voltage and each logic gate output. Any [[logic gate]], including the [[logic gate#inverter|logical inverter]], can then be implemented by designing a network of parallel and/or series circuits, such that if the desired output for a certain combination of [[boolean data type|boolean]] input values is [[boolean logic|zero]] (or [[boolean logic|false]]), the PDN will be active, meaning that at least one transistor is allowing a current path between the negative supply and the output. This causes a voltage drop over the load, and thus a low voltage at the output, representing the ''zero.''
[[Image:NMOS NOR WITH RESISTIVE LOAD.PNG|200px|thumb|The R-pulled circuit acts like a NOR gate that sinks OUT to the GND.]]

As an example, here is a [[Logical NOR|NOR]] gate implemented in schematic NMOS.  If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low (logic 0, = False).  When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which occurs only when both A and B are low, thus satisfying the truth table of a NOR gate:

{| class="wikitable"N-type metal–oxide–semiconductor logic uses n-type field-effect transistors (MOSFETs) to implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity saturation. 
! A !! B !! A NOR B
|- align=center
| 0 || 0 || 1
|- align=center
| 0 || 1 || 0
|- align=center
| 1 || 0 || 0
|- align=center
| 1 || 1 || 0
|}

A MOSFET can  be made to operate as a resistor, so the whole circuit can be made with n-channel MOSFETs only. NMOS circuits are slow to transition from low to high.  When transitioning from high to low, the transistors provide low resistance, and the capacitive charge at the output drains away very quickly (similar to discharging a capacitor through a very low resistor). But the resistance between the output and the positive supply rail is much greater, so the low to high transition takes longer (similar to charging a capacitor through a high value resistor). Using a resistor of lower value will speed up the process but also increases static power dissipation. However, a better (and the most common) way to make the gates faster is to use [[Depletion-load NMOS logic|depletion-mode]] transistors instead of [[MOSFET|enhancement-mode]] transistors as loads. This is called [[depletion-load NMOS logic]].

==References==
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==External links==
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{{DEFAULTSORT:Nmos Logic}}
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