Editing Motorola 68000 series

{{short description|Series of 32 bit CISC microprocessors}}
{{About|the family of microprocessors|the first such microprocessor in that family|Motorola 68000}}<!-- This template used in lieu of [[Template:Redirect]] because it produces better text.  -->

{{Infobox CPU architecture
| name       = Motorola 68000 series
| designer   = [[Motorola]]
| bits       = [[32-bit computing|32-bit]]
| introduced = {{Start date and age|1979}}
| version    = 
| design     = [[Complex instruction set computer|CISC]]
| type       = 
| encoding   = 
| branching  = [[Status register|Condition code]]
| endianness = Big
| page size  = 
| extensions = 
| open       = 
| registers  = {{unbulleted list |
8 × 32-bit data registers |
7 × 32-bit address registers |
stack pointer (address register 7) |
8 × 80-bit floating-point registers if FP present
}}
}}
The '''Motorola 68000 series''' (also known as '''680x0''', '''m68000''', '''m68k''', or '''68k''') is a family of [[32-bit computing|32-bit]] [[complex instruction set computer]] (CISC) [[microprocessor]]s. During the 1980s and early 1990s, they were popular in [[personal computer]]s and [[workstation]]s and were the primary competitors of [[Intel]]'s [[x86]] microprocessors. They were best known as the processors used in the early Apple [[Mac (computer)|Macintosh]], the Sharp [[X68000]], the Commodore [[Amiga]], the [[Sinclair QL]], the [[Atari ST]] and [[Atari Falcon|Falcon]], the [[Atari Jaguar]], the [[Sega Genesis]] (Mega Drive) and [[Sega CD]], the [[Philips CD-i]], the [[CP System|Capcom System I]] (Arcade), the [[AT&T UNIX PC]], the Tandy [[TRS-80 Model II#Model 16B and Tandy 6000|Model 16/16B/6000]], the Sun Microsystems [[Sun-1]], [[Sun-2]] and [[Sun-3]], the [[NeXT Computer]], [[NeXTcube]], [[NeXTstation]], and [[NeXTcube Turbo]], early [[Silicon Graphics]] IRIS workstations, the [[Aesthedes]], computers from [[MASSCOMP]], the [[Texas Instruments]] [[TI-89]]/[[TI-92]] calculators, the [[Palm Pilot]] (all models running Palm OS 4.x or earlier), the [[Control Data Corporation]] [[CDCNET]] Device Interface, the [[VTech]] Precomputer Unlimited and the [[Space Shuttle]]. Although no modern desktop computers are based on processors in the 680x0 series, derivative processors are still widely used in [[embedded system]]s.

[[Motorola]] ceased development of the 680x0 series architecture in 1994, replacing it with the [[PowerPC]] [[RISC]] architecture, which was developed in conjunction with [[IBM]] and [[Apple Computer]] as part of the [[AIM alliance]].

== Family members ==
* Generation one (internally 16/32-bit, and produced with [[8-bit computing|8-]], [[16-bit computing|16-]], and [[32-bit computing|32-bit]] interfaces)
** [[Motorola 68000|68000]]
** [[Motorola 68EC000|68EC000]]
** [[Motorola 68SEC000|68SEC000]]
** [[Motorola 68HC000|68HC000]]
** [[Motorola 68008|68008]]
** [[Motorola 68010|68010]]
** [[Motorola 68012|68012]]
* Generation two (internally fully 32-bit)
** [[Motorola 68020|68020]]
** [[Motorola 68EC020|68EC020]]
** [[Motorola 68030|68030]]
** [[Motorola 68EC030|68EC030]]
* Generation three ([[instruction pipeline|pipelined]])
** [[Motorola 68040|68040]]
** [[Motorola 68EC040|68EC040]]
** [[Motorola 68LC040|68LC040]]
* Generation four ([[superscalar]])
** [[Motorola 68060|68060]]
** 68EC060
** 68LC060
* Others
** [[Freescale 683XX]] (CPU32 aka 68330, 68360 aka [[QUICC]])
** [[Freescale ColdFire]]
** [[Freescale DragonBall]]
** [[Philips 68070]]
** APOLLO CORE 68080 <ref>{{cite web | url=http://www.apollo-core.com/index.htm?page=features | title=APOLLO 68080 - High Performance Processor }}</ref>

==Improvement history==
[[Motorola 68010|68010]]:
* Virtual memory support (restartable instructions)
* 'Loop mode' for faster string and memory library primitives
* Multiply instruction uses 14 fewer clock ticks
* 2&nbsp;[[GiB]] directly accessible memory ([[Motorola 68012|68012]] variant)

[[Motorola 68020|68020]]:
* 32-bit address & [[arithmetic logic unit]] (ALU)
* Three stage [[Pipeline (computing)|pipeline]]
* Instruction [[CPU cache|cache]] of 256 bytes
* Unrestricted word and longword data access (see [[Data structure alignment|alignment]])
* 8× [[multiprocessing]] ability
* Larger multiply (32×32 -> 64 bits) and divide (64÷32 -> 32 bits quotient and 32 bits remainder) instructions, and bit field manipulations
* Addressing modes added [[Addressing mode#Scaled|scaled indexing]] and another level of [[Addressing mode#Memory indirect|indirection]]
* Low cost, EC = 24-bit address

[[Motorola 68030|68030]]:
* Split instruction and data cache of 256&nbsp;[[byte]]s each
* On-chip [[memory management unit]] (MMU) ([[Motorola 68851|68851]])
* Low cost EC = No MMU
* Burst Memory Interface

[[Motorola 68040|68040]]:
* Instruction and data caches of 4&nbsp;[[Kibibyte|KB]] each
* Six stage pipeline
* On-chip [[floating-point unit]] (FPU)
* FPU lacks IEEE [[transcendental function]] ability
* FPU emulation works with 2E71M and later chip revisions
* Low cost LC = No FPU
* Low cost EC = No FPU or MMU

[[Motorola 68060|68060]]:
* Instruction and data caches of 8&nbsp;KB each
* 10 stage pipeline
* Two cycle integer multiplication unit
* [[Branch predictor|Branch prediction]]
* Dual instruction pipeline
* Instructions in the [[address generation unit]] (AGU) and thereby supply the result two cycles before the ALU
* Low cost LC = No FPU
* Low cost EC = No FPU or MMU

==Feature map==
{| class="wikitable"
|- 
! Year !! CPU !! [[Chip carrier|Package]] !! Frequency (max) [in MHz] !! Address bus bits !! [[Memory management unit|MMU]] !! [[Floating-point unit|FPU]]
|-
| 1979 || [[Motorola 68000|68000]] || {{nowrap|64-pin [[dual in-line package]] (DIP)}}, {{nowrap|64-pin SPDIP}}, {{nowrap|68-pin PLCC}}, {{nowrap|68-pin CLCC}}, {{nowrap|68-pin [[pin grid array]] (PGA)}}, {{nowrap|64-pin QFP}}, {{nowrap|68-pin QFP}}<ref>{{cite web |url=http://www.cpu-world.com/CPUs/68000/index.html |website=CPU-World |title=Motorola 68000 microprocessor family |access-date=2012-11-17}}</ref> || 8–50<ref>{{cite web | url=http://amigaprj.blogspot.com/2015/07/amiga-500-accelerator-card-with-68hc000.html | title=Amiga projects: Amiga 500 68HC000 accelerator running at 50 MHZ | date=12 July 2015 }}</ref> || 24 || - || -
|-
| 1982 || [[Motorola 68008|68008]] || {{nowrap|48-pin [[dual in-line package]] (DIP)}}, {{nowrap|52-pin PLCC}}<ref>{{cite web |url=https://www.cpu-world.com/CPUs/68008/index.html |website=CPU-World |title=Motorola 68008 microprocessor family |access-date=2012-11-17}}</ref> || 8–16.67 || 24 || - || -
|-
| 1982 || [[Motorola 68010|68010]] || {{nowrap|64-pin DIP}}, {{nowrap|68-pin PLCC}}, {{nowrap|68-pin PGA}}<ref>{{cite web |url=http://www.cpu-world.com/CPUs/68010/index.html |website=CPU-World |title=Motorola 68010 (MC68010) family |access-date=2012-11-17}}</ref> || {{nowrap|8–16.67}} || 24 || [[Motorola 68451|68451]] || -
|-
| 1982 || [[Motorola 68012|68012]] || {{nowrap|84-pin PGA}}<ref>{{cite web |url=https://www.cpu-world.com/CPUs/68012/index.html |website=CPU-World |title=Motorola 68012 (MC68012) family |access-date=2012-11-17}}</ref> || {{nowrap|8–12.5}} || 31 || [[Motorola 68451|68451]] || -
|-
| 1984 || [[Motorola 68020|68020]] || {{nowrap|114-pin PGA}}<ref>{{cite web |url=http://www.cpu-world.com/CPUs/68020/index.html |website=CPU-World |title=Motorola 68020 (MC68020) microprocessor family |access-date=2012-12-17}}</ref> || {{nowrap|12.5–33.33}} || 32 || [[Motorola 68851|68851]] || [[Motorola 68881|68881]]
|-
| - || [[Motorola 68020|68'''EC'''020]] || {{nowrap|100-pin [[Quad Flat Package]] (QFP)}}<ref>{{cite web |url=http://www.cpu-world.com/CPUs/68020/Motorola-MC68EC020FG16.html |website=CPU-World |title=Motorola MC68EC020FG16 |access-date=2012-11-17}}</ref> || {{nowrap|16.7–25}} || 24 || - || -<!--CHECK, contradictions in src!-->
|-
| 1987 || [[Motorola 68030|68030]] || {{nowrap|132-pin QFP}} (max {{nowrap|33 MHz}}), {{nowrap|128-pin PGA}}<ref>{{cite web |url=http://www.cpu-world.com/CPUs/68030/index.html |website=CPU-World |title=Motorola 68030 (MC68030) microprocessor family |access-date=2012-11-17}}</ref> || {{nowrap|16–50}} || 32 || MMU || [[Motorola 68881|68881]]
|-
|      || [[Motorola 68030|68'''EC'''030]] || {{nowrap|132-pin QFP}}, {{nowrap|128-pin PGA}} || {{nowrap|25-40<ref>{{cite web |url=https://www.cpu-world.com/CPUs/68030/Motorola-MC68EC030RP25%20-%20MC68EC030RP25B%20-%20MC68EC030RP25C.html |website=CPU-World |title=Motorola MC68EC030RP25 / MC68EC030RP25B / MC68EC030RP25C}}</ref><ref>{{cite web |url=https://www.cpu-world.com/CPUs/68030/Motorola-MC68EC030RP40%20-%20MC68EC030RP40B%20-%20MC68EC030RP40C.html |website=CPU-World |title=Motorola MC68EC030RP40 / MC68EC030RP40B / MC68EC030RP40C}}</ref>}} || 32 || - || [[Motorola 68881|68881]]
|- 
| 1991 || [[Motorola 68040|68040]] || {{nowrap|179-pin PGA}},<ref>{{cite web |url=http://www.cpu-world.com/CPUs/68040/index.html |website=CPU-World |title=Motorola 68040 (MC68040) microprocessor family |access-date=2012-11-17}}</ref> {{nowrap|184-pin QFP}}<ref name=fs040>{{cite web |url=http://cache.freescale.com/files/32bit/doc/ref_manual/MC68040UM.pdf |website=freescale.com |title=M68040 User's Manual |archive-url=https://web.archive.org/web/20160417123708/http://cache.freescale.com/files/32bit/doc/ref_manual/MC68040UM.pdf |archive-date=17 April 2016 |access-date=2007-05-08}}</ref> || {{nowrap|20–40}} || 32 || MMU || FPU
|-
|      || [[Motorola 68040|68'''LC'''040]] || {{nowrap|PGA}},<ref name=fs040/> {{nowrap|184-pin QFP}}<ref name=fs040/> || {{nowrap|20–33}} || 32 || MMU || -
|-
|      || [[Motorola 68040|68'''EC'''040]] ||  || {{nowrap|20–33}}<ref name=fs040/> || 32 || -   || -
|-
| 1994 || [[Motorola 68060|68060]] || {{nowrap|206-pin PGA}}<ref name=cw060>{{cite web |url=http://www.cpu-world.com/CPUs/68060/index.html |website=CPU-World |title=Motorola 68060 processor family |access-date=2012-11-22}}</ref><ref name=fs060>{{cite web| url=http://cache.freescale.com/files/32bit/doc/ref_manual/MC68060UM.pdf |website=freescale.com |title=M68060 User's Manual |access-date=2010-07-28 |archive-url=https://web.archive.org/web/20160823214139/http://cache.freescale.com/files/32bit/doc/ref_manual/MC68060UM.pdf |archive-date=23 August 2016}}</ref> || {{nowrap|50–133<ref name="happy-birthday-arne">{{Cite web |url=http://www.natami.net/knowledge.php?b=1&note=39600 |title=Happy Birthday Arne! |website=NatAmi Knowledge Forum |access-date=2024-06-07 |archive-date=2011-06-13 |archive-url=https://web.archive.org/web/20110613173724/http://www.natami.net/knowledge.php?b=1&note=39600 |url-status=dead }}</ref><ref name="68060 mask">{{cite web | url=http://www.amigawiki.org/doku.php?id=de:parts:68060_mask | title=68060 Masken und Fakes [amiga-wiki] }}</ref>}} || 32 || MMU || FPU
|-
|      || [[Motorola 68060|68'''LC'''060]] || {{nowrap|206-pin PGA}},<ref name=cw060/><ref name=fs060/> 208-pin QFP<ref>[https://archive.org/stream/amigaformatmagazine-126/Amiga_Format_Issue_126_1999_08_Future_Publishing_GB#page/n49/mode/2up Archive.org - Amiga Format review of 68LC060-based accelerator board]{{dead link|date=September 2021}}</ref> || {{nowrap|50–133<ref name="happy-birthday-arne" /><ref name="68060 mask" />}} || 32 || MMU || -
|-
|      || [[Motorola 68060|68'''EC'''060]] || {{nowrap|206-pin PGA}}<ref name=cw060/><ref name=fs060/> || {{nowrap|50–133<ref name="happy-birthday-arne" /><ref name="68060 mask" />}} || 32 || - || -
|}

==Uses==
[[File:Sega-Genesis-Mod1-Set.jpg|thumb|The Genesis has a 68000 clocked at 7.67&nbsp;MHz as its main CPU.]]

The 680x0 line of processors has been used in a variety of systems, from high-end [[Texas Instruments]] calculators (the [[TI-89]], [[TI-92]], and [[Voyage 200]] lines) to all of the members of the [[Palm Pilot]] series that run Palm OS 1.x to 4.x (OS 5.x is [[ARM architecture|ARM]]-based), and even [[radiation hardened|radiation-hardened]] versions in the critical control systems of the [[Space Shuttle]].

The 680x0 CPU family became most well known for powering [[desktop computer]]s and [[video game console]]s such as the [[Macintosh 128K]], [[Amiga]], [[Sinclair QL]], [[Atari ST]], [[Sega Genesis|Genesis / Mega Drive]], [[Neo Geo (system)|NG AES]]/[[Neo Geo CD]], [[CDTV]]. They were the processors of choice in the 1980s for [[Unix]] [[workstation]]s and [[Server (computing)|servers]] such as AT&T's [[AT&T UNIX PC|UNIX PC]], Tandy's [[TRS-80 Model II#Model 16B and Tandy 6000|Model 16/16B/6000]], Sun Microsystems' [[Sun-1]], [[Sun-2]], [[Sun-3]], [[NeXT#1987–1993: NeXT Computer|NeXT Computer]], [[Silicon Graphics]] (SGI), and numerous others. 
The [[Sega Saturn|Saturn]] uses the 68000 for audio processing and other I/O tasks, while the [[Atari Jaguar|Jaguar]] includes a 68000 intended for basic system control and input processing, but was frequently used for running game logic. Many arcade boards also use 68000 processors including those from Capcom, SNK, and Sega.

The first several versions of Adobe's [[PostScript]] interpreters were 68000-based. The 68000 in the Apple [[LaserWriter]] and LaserWriter Plus was clocked faster than the version used then in Macintosh computers. A fast 68030 in later PostScript interpreters, including the standard resolution LaserWriter IIntx, IIf and IIg (also 300 dpi), the higher resolution LaserWriter Pro 600 series (usually 600&nbsp;dpi, but limited to 300&nbsp;dpi with minimum RAM installed) and the very high resolution [[Linotronic]] imagesetters, the 200PS (1500+&nbsp;dpi) and 300PS (2500+&nbsp;dpi). Thereafter, Adobe generally preferred a RISC for its processor, as its competitors, with their PostScript clones, had already gone with RISCs, often an AMD 29000-series. The early 68000-based Adobe PostScript interpreters and their hardware were named for [[Cold War]]-era U.S. rockets and missiles: Atlas, Redstone, etc.

[[Microcontroller]]s derived from the 68000 family have been used in a huge variety of applications. [[CPU32]] and [[Freescale ColdFire|ColdFire]] microcontrollers have been manufactured in the millions as automotive engine controllers.

Many proprietary video editing systems used 68000 processors, such as the MacroSystem Casablanca, which was a black box with an easy to use graphic interface (1997). It was intended for the amateur and hobby videographer market. It is also worth noting its earlier, bigger and more professional counterpart, the "DraCo" (1995). The groundbreaking [[Quantel Paintbox]] series of early based 24-bit paint and effects system was originally released in 1981 and during its lifetime it used nearly the entire range of 68000 family processors, with the sole exception of the 68060, which was never implemented in its design. Another contender in the video arena, the Abekas 8150 DVE system, used the 680EC30, and the Play Trinity, later renamed Globecaster, uses several 68030s. The Bosch FGS-4000/4500 Video Graphics System manufactured by Robert Bosch Corporation, later BTS (1983), used a 68000 as its main processor; it drove several others to perform 3D animation in a computer that could easily apply Gouraud and Phong shading. It ran a modified [[VERSAdos|Motorola VERSAdos]] operating system.

==Architecture==
{| class="infobox" style="font-size:88%;width:39em;"
|-
|+ Motorola 68000 series registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:left"  | <sup>3</sup><sub>1</sub>
| style="width:60px; text-align:center"| ...
| style="width:10px; text-align:right" | <sup>2</sup><sub>3</sub>
| style="width:60px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:60px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:60px; text-align:center"| ...
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="10" | '''Data registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D0
| style="background:white; color:black" | Data 0
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D1
| style="background:white; color:black" | Data 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D2
| style="background:white; color:black" | Data 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D3
| style="background:white; color:black" | Data 3
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D4
| style="background:white; color:black" | Data 4
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D5
| style="background:white; color:black" | Data 5
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D6
| style="background:white; color:black" | Data 6
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| D7
| style="background:white; color:black" | Data 7
|-
|colspan="10" | '''Address registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A0
| style="background:white; color:black" | Address 0
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A1
| style="background:white; color:black" | Address 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A2
| style="background:white; color:black" | Address 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A3
| style="background:white; color:black" | Address 3
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A4
| style="background:white; color:black" | Address 4
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A5
| style="background:white; color:black" | Address 5
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A6
| style="background:white; color:black" | Address 6
|-
|colspan="10" | '''Stack pointers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A7 / USP
| style="background:white; color:black;"| Stack&nbsp;Pointer (user)
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| A7' / SSP
| style="background:white; color:black;"| Stack&nbsp;Pointer (supervisor)
|-
|colspan="10" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="9"| PC
| style="background:white; color:black;"| Program&nbsp;Counter
|}
|-
|
{| style="font-size:88%;"
|-
|colspan="17" | '''Status Register'''
|-
| style="width:98px; text-align:center"| 
| style="width:10px; text-align:center"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- style="background:silver;color:black"
| style="background:white;"| 
| style="text-align:center" colspan="2"| T
| style="text-align:center"| S
| style="text-align:center"| M
| style="text-align:center"| 0
| style="text-align:center" colspan="3"| I
| style="text-align:center"| 0
| style="text-align:center"| 0
| style="text-align:center"| 0
| style="text-align:center"| X
| style="text-align:center"| [[Sign flag|N]]
| style="text-align:center"| [[Zero flag|Z]]
| style="text-align:center"| [[Overflow flag|V]]
| style="text-align:center"| [[Carry flag|C]]
| style="background:white; color:black" | '''SR'''
|}
|}

People who are familiar with the [[PDP-11]] or [[VAX]] usually feel comfortable with the 68000 series. With the exception of the split of general-purpose registers into specialized data and address registers, the 68000 architecture is in many ways a 32-bit PDP-11.

It had a more [[orthogonal instruction set]] than those of many processors that came before (e.g., 8080) and after (e.g., x86). That is, it was typically possible to combine operations freely with operands, rather than being restricted to using certain addressing modes with certain instructions. This property made programming relatively easy for humans, and also made it easier to write code generators for compilers.

The 68000 series has eight 32-bit general-purpose data [[processor register|registers]] (D0-D7), and eight address registers (A0-A7). The last address register is the [[stack (data structure)|stack pointer]], and assemblers accept the label SP as equivalent to A7.

In addition, it has a 16-bit status register. The upper 8 bits is the system byte, and modification of it is privileged. The lower 8 bits is the user byte, also known as the condition code register (CCR), and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes to record their results for use by later conditional jumps. The condition code bits are "zero" (Z), "carry" (C), "overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention, because it is separate from the [[carry flag]]. This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry for flow-of-control and linkage.

While the 68000 had a 'supervisor mode', it did not meet the [[Popek and Goldberg virtualization requirements]] due to the single instruction 'MOVE from SR', which copies the status register to another register, being unprivileged but sensitive. In the [[Motorola 68010]] and later, this was made privileged, to better support virtualization software.

<!-- Please make the spelling of instructions consistent. I don't know what some of these are acronyms for, so I'm not sure which letters should be capitalized. -->
The 68000 series [[instruction set]] can be divided into the following broad categories:

* Load and store (MOVE)
* [[Arithmetic]] (ADD, SUB, MULS, MULU, DIVS, DIVU)
* [[Bitwise operation|Bit shifting]] (ASL, ASR, LSL, LSR)
* Bit rotation (ROR, ROL, ROXL, ROXR)
<!-- Perhaps the two above should be merged (also since "bitwise operation" is one article). What are the shifting instructions? -->
* [[Logic operation]]s (AND, OR, NOT, EOR)
* Type conversion ([[byte]] to [[Word (data type)|word]] and ''vice versa'')
* [[Conditional branch|Conditional]] and [[unconditional branch]]es (BRA, Bcc - BEQ, BNE, BHI, BLO, BMI, BPL, etc.)
* [[Subroutine]] invocation and return (BSR, RTS) 
* [[Call stack|Stack]] management (LINK, UNLK, PEA)
* Causing and responding to [[interrupt]]s
* [[Exception handling]]
* There is no equivalent to the x86 [[CPUID]] instruction to determine what CPU or MMU or FPU is present.

The [[Motorola 68020]] added some new instructions that include some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system (which were removed in the 68060), some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger multiply (32×32→64 bits) and divide (64÷32→32 bits quotient and 32 bits remainder) instructions, and bit field manipulations.

The standard [[addressing mode]]s are:

*Register direct
**Data register, e.g. "D0"
**Address register, e.g. "A0"
*Register indirect
**Simple address, e.g. (A0)
**Address with post-increment, e.g. (A0)+
**Address with pre-decrement, e.g. −(A0)
**Address with a 16-bit signed offset, e.g. 16(A0)
**Register indirect with index register and 8-bit signed offset e.g. 8(A0,D0) or 8(A0,A1)
*:For (A0)+ and −(A0), the actual increment or decrement value is dependent on the operand size: a byte access adjusts the address register by 1, a word by 2, and a long by 4.
*PC (program counter) relative with displacement
**Relative 16-bit signed offset, e.g. 16(PC). This mode was very useful for position-independent code.
**Relative with 8-bit signed offset with index, e.g. 8(PC,D2)
*Absolute memory location
**Either a number, e.g. "$4000", or a symbolic name translated by the assembler
**Most assemblers used the "$" symbol for [[hexadecimal]], instead of "0x" or a trailing H.
**There were 16 and 32-bit versions of this addressing mode
*Immediate mode
**Data stored in the instruction, e.g. "#400"
*Quick immediate mode
**3-bit unsigned (or 8-bit signed with moveq) with value stored in opcode
**In addq and subq, 0 is the equivalent to 8
**e.g. moveq #0,d0 was quicker than clr.l d0 (though both made D0 equal to 0)

Plus: access to the [[status register]], and, in later models, other special registers.

The Motorola 68020 added a [[Addressing mode#Scaled|scaled indexing]] address mode, and added another level of [[Addressing mode#Memory indirect|indirection]] to many of the pre-existing modes.

Most instructions have dot-letter suffixes, permitting operations to occur on 8-bit bytes (".b"), 16-bit words (".w"), and 32-bit longs (".l").

Most instructions are '''[[wikt:dyadic|dyadic]]''', that is, the operation has a source, and a destination, and the destination is changed. Notable instructions were:

*Arithmetic: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU, DIVS, NEG (additive negation), and CMP (a comparison done by subtracting the arguments without storing the result, setting the status bits)
*[[Binary-coded decimal]] arithmetic: ABCD, NBCD, and SBCD
*Logic: EOR (exclusive or), AND, NOT (logical not), OR (inclusive or)
*Shifting: (logical, i.e. right shifts put zero in the most-significant bit) LSL, LSR, ([[arithmetic shift]]s, i.e. sign-extend the most-significant bit) ASR, ASL, (rotates through eXtend and not) ROXL, ROXR, ROL, ROR
*[[Bit test and manipulation]] in memory or data register: BSET (set to 1), BCLR (clear to 0), BCHG (invert) and BTST (no change). All of these instructions first test the destination bit and set (clear) the CCR Z bit if the destination bit is 0 (1), respectively.
*[[Multiprocessing]] control: TAS, [[test-and-set]], performed an indivisible bus operation, permitting [[semaphore (programming)|semaphore]]s to be used to synchronize several processors sharing a single memory
*Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to subroutine), RTS (return from [[subroutine]]), RTE (return from [[Interrupt|exception]], i.e. an interrupt), TRAP (trigger a software exception similar to software interrupt), CHK (a conditional software exception)
*Branch: Bcc (where the "cc" specified one of 14 tests of the condition codes in the status register: equal, greater than, less-than, carry, and most combinations and logical inversions, available from the status register). Of the remaining two possible conditions, always true and always false, BRA (branch always) has a separate mnemonic, and BSR (branch to subroutine) takes the encoding that would otherwise have been 'branch never'.
*Decrement-and-branch: DBcc (where "cc" was as for the branch instructions), which, provided the condition was '''false''', decremented the low word of a D-register and, if the result was not -1 ($FFFF), branched to a destination. This use of −1 instead of 0 as the terminating value allowed the easy coding of loops that had to do nothing if the count was 0 to start with, with no need for another check before entering the loop. This also facilitated nesting of DBcc.

==68050 and 68070==
{{Unreferenced section|date=October 2013}}

Motorola mainly used even numbers for major revisions to the CPU core such as 68000, 68020, 68040 and 68060. The 68010 was a revised version of the 68000 with minor modifications to the core, and likewise the 68030 was a revised 68020 with some more powerful features, none of them significant enough to classify as a major upgrade to the core.

The 68050 was reportedly "a minor upgrade of the 68040" that lost a battle for resources within Motorola, competing against projects that had been scheduled to succeed it: the 0.5μm, low-power, low-cost "LP040", and the superscalar, superpipelined "Q", borrowing from the 88110 and anticipated as the 68060.<ref name="unigramx19920413_motorola">{{ cite news | url=https://archive.org/details/UnigramX1992366-416/page/n100/mode/1up | title=Motorola 68060 "Could Impact PowerPC" | work=Unigram/X | date=13 April 1992 | access-date=22 December 2024 | pages=3 }}</ref> Subsequent reports indicated that Motorola had considered the 68050 as not meriting the necessary investment in production of the part.<ref name="unigramx19930419_motorola">{{ cite news | url=https://archive.org/details/UnigramX1993417-467/page/n120/mode/1up | title=Motorola to Sample 68060 in July | work=Unigram/X | date=19 April 1993 | access-date=22 December 2024 | pages=3 }}</ref> Odd-numbered releases had always been reactions to issues raised within the prior even numbered part; hence, it was generally expected that the 68050 would have reduced the 68040's power consumption (and thus heat dissipation), improved exception handling in the FPU, used a smaller feature size and optimized the microcode in line with program use of instructions. Many of these optimizations were included with the 68060 and were part of its design goals. For any number of reasons, likely that the 68060 was in development, that the Intel 80486 was not progressing as quickly as Motorola assumed it would, and that 68060 was a demanding project, the 68050 was cancelled early in development.

There is also no revision of the [[68060]], as Motorola was in the process of shifting away from the 68000 and [[88000|88k]] processor lines into its new [[PowerPC]] business, so the 68070 was never developed. Had it been, it would have been a revised 68060, likely with a superior FPU (pipelining was widely speculated upon on Usenet).

There was a CPU with the [[68070]] designation, which was a licensed and somewhat slower version of the 16/32-bit 68000 with a basic DMA controller, [[I²C]] host and an on-chip serial port. This 68070 was used as the main CPU in the [[Philips]] [[CD-i]]. This CPU was, however, produced by [[Philips]] and not officially part of Motorola's 680x0 lineup.

Motorola had announced a product roadmap beyond the 68060 featuring the 68080 rated at 200-350 MIPS, due by 1995, and a product rated at 800 MIPS, possibly with the name 68100, by 2000.<ref name="unigramx19930419_motorola"/>

==Last generation==
The 4th-generation [[68060]] provided equivalent functionality (though not instruction-set-architecture compatibility) to most of the features of the Intel [[P5 (microarchitecture)|P5 microarchitecture]].

==Other variants==
The Personal Computers [[XT/370]] and [[AT/370]] [[PC-based IBM-compatible mainframes]] each included two modified Motorola 68000 processors with custom [[microcode]] to emulate [[IBM System 370|S/370]] mainframe instructions.<ref>
{{cite web|url=https://priorart.ip.com/IPCOM/000059679# |title=Implementation of IBM System 370 Via Co-Microprocessors/The Co-Processor... - IPCOM000059679D - IP.com |publisher=Priorartdatabase.com |access-date=2020-07-23}}
</ref><ref name=Mueller92>{{cite book 
| first      = Scott 
| last       = Mueller 
| title      = Upgrading and Repairing PCs, Second Edition 
| publisher  = Que Books 
| year       = 1992 
| isbn       = 0-88022-856-3 
| pages      = 73–75,94 
| url        = https://archive.org/details/upgradingrepairi0000muel_2ndedition/page/72/mode/2up 
| url-access = registration}}
</ref>

An Arizona-based company, [[Edge Computer Corp]], reportedly founded by former Honeywell designers, produced processors compatible with the 68000 series, these being claimed as having "a three to five times performance – and {{nowrap|18 to 24 months' time}} – advantage" over Motorola's own products.<ref name="techmonitor19870827_edge">{{ cite news | url=https://techmonitor.ai/technology/olivetti_to_launch_68020_compatible_mini_from_edge_in_november | title=Olivetti "to Launch 68020-Compatible Mini from Edge in November" | work=Tech Monitor | date=27 August 1987 | access-date=3 June 2022 }}</ref> In 1987, the company introduced the Edge 1000 range of "32-bit superminicomputers implementing the Motorola instruction set in the Edge mainframe architecture", employing two independent pipelines - an instruction fetch pipeline (IFP) and operand executive pipeline (OEP) - relying on a branch prediction unit featuring a 4096-entry branch cache, retrieving instructions and operands over multiple buses.<ref name="computer198709_edge">{{ cite magazine | url=https://archive.org/details/computer-magazine-1987-09/page/n108/mode/1up | title=Edge supermini delivers RISC performance with CISC instruction set | magazine=Computer | date=September 1987 | access-date=18 June 2022 | pages=107 }}</ref> An agreement between Edge Computer and Olivetti subsequently led to the latter introducing products in its own "Linea Duo" range based on Edge Computer's machines.<ref name="techmonitor19871115_edge">{{ cite news | url=https://techmonitor.ai/technology/olivetti_to_launch_models_of_the_edge_computer_machines_as_linea_duo | title=Olivetti to Launch Models of the Edge Computer Machines as Linea Duo | work=Tech Monitor | date=15 November 1987 | access-date=3 June 2022 }}</ref> The company was subsequently renamed to Edgcore Technology Inc.<ref name="unixreview198812_edge">{{ cite magazine | url=https://archive.org/details/sim_unix-review_1988-12_6_12/page/12/mode/1up | title=Currents | magazine=UNIX Review | date=December 1988 | access-date=5 June 2022 | pages=8,10,12-13 }}</ref>{{rp|pages=12}} (also reported as Edgecore Technology Inc.<ref name="techmonitor19880926_edgecore">{{cite news | url=https://techmonitor.ai/technology/edge_computer_corp_read_edgecore_technology_inc | title=Edge Computer Corp, Read Edgecore Technology Inc. | work=Tech Monitor | date=26 September 1988 | access-date=3 June 2022 | archive-date=11 August 2022 | archive-url=https://web.archive.org/web/20220811115158/https://techmonitor.ai/technology/edge_computer_corp_read_edgecore_technology_inc | url-status=dead }}</ref>). Edgcore's deal with [[Olivetti]] in 1987 to supply the company's E1000 processor was followed in 1989 by another deal with [[Philips Telecommunications Data Systems]] to supply the E2000 processor, this supporting the 68030 instruction set and reportedly offering a performance rating of 16 VAX MIPS.<ref name="electronicnews19890313_edgcore">{{ cite magazine | url=https://archive.org/details/sim_electronic-news_1989-03-13_35_1749/page/n13/mode/1up | title=Edgcore Wins $20M Philips Contract, Four-Year Agreement for E2000 CPUs | magazine=Electronic News | date=13 March 1989 | access-date=5 June 2022 | pages=14 }}</ref> Similar deals with [[Nixdorf Computer]] and [[Hitachi]] were also signed in 1989.<ref name="electronicnews19890327_edgcore">{{ cite magazine | url=https://archive.org/details/sim_electronic-news_1989-03-27_35_1751/page/n15/mode/1up | title=Data Topics | magazine=Electronic News | date=27 March 1989 | access-date=5 June 2022 | pages=12 }}</ref><ref name="electronicnews19890717_edgcore"/>

Edge Computer reportedly had an agreement with Motorola.<ref name="techmonitor19880926_edgecore"/> Despite increasing competition from RISC products, Edgcore sought to distinguish its products in the market by emphasising its "alliance" with Motorola, employing a marketing campaign drawing from Aesop's fables with "the fox (Edgecore) who climbs on the back of the stallion (Motorola) to pluck fruit off the higher branches of the tree".<ref name="electronics198904_marketing">{{ cite magazine | url=https://archive.org/details/electronics-1989_04/page/100/mode/1up | title=High-Tech Marketing: A Balancing Act Between Style and Substance | magazine=Electronics | last1=Waller | first1=Larry | date=April 1989 | access-date=5 June 2022 | pages=100–102 }}</ref> Other folktale advertising themes such as [[Little Red Riding Hood]] were employed.<ref name="electronics19880428_edge">{{ cite magazine | url=https://archive.org/details/electronics-1988_04_28/page/70/mode/2up | title=Thinking of getting into bed with RISC? | magazine=Electronics |type=Edge Computer advertisement | date=28 April 1988 | access-date=18 October 2022 | pages=70–71 }}</ref> With the company's investors having declined to finance the company further, and with a number of companies having been involved in discussions with other parties, [[Arix Corp]]. announced the acquisition of Edgcore in July 1989.<ref name="electronicnews19890717_edgcore">{{ cite magazine | url=https://archive.org/details/sim_electronic-news_1989-07-17_35_1767/page/n21/mode/1up | title=Arix May Buy Edgcore | magazine=Electronic News | date=17 July 1989 | access-date=5 June 2022 | pages=20 }}</ref> Arix was reportedly able to renew its deal with Hitachi in 1990, whereas the future of previous deals with Olivetti and Philips remained in some doubt after the acquisition of Edgcore.<ref name="electronicnews19901001_hitachi">{{ cite magazine | url=https://archive.org/details/sim_electronic-news_1990-10-01_36_1829/page/n19/mode/1up | title=Hitachi Discloses Price, Specs for Latest DASD | magazine=Electronic News | date=1 October 1990 | access-date=5 June 2022 | pages=18 }}</ref>

In 1992, a company called [[International Meta Systems]] (IMS) announced a RISC-based CPU, the {{nowrap|IMS 3250}}, that could reportedly emulate the "Intel 486 or Motorola 68040 at full native speeds and at a fraction of their cost". Clocked at {{val|100|ul=MHz}}, emulations had supposedly been developed of a {{val|25|u=MHz}} 486 and {{val|30|u=MHz}} 68040, including floating-point unit support, with the product aiming for mid-1993 production at a per-unit cost of {{val|p=$|50 |to| 60}}.<ref name="byte199211_ims3250">{{ cite magazine | url=https://archive.org/details/eu_BYTE-1992-11_OCR/page/n41/mode/1up | magazine=Byte | title=New RISC Chip to Emulate 486 and 68040 | last1=Halfhill | first1=Tom R. | date=November 1992 | access-date=12 June 2022 | pages=36 }}</ref> Amidst the apparent proliferation of emulation support in processors such as the [[PowerPC 600#PowerPC 615|PowerPC 615]], in 1994, IMS had reportedly filed a patent on its emulation technology but had not found any licensees.<ref name="byte199409_ims">{{ cite magazine | url=https://archive.org/details/ByteV19N9/page/n41/mode/1up | title=IMS Takes On 80x86 Emulation | magazine=Byte | last1=Ryan | first1=Bob | date=September 1994 | access-date=12 June 2022 | pages=38 }}</ref> Repeated delays to the introduction of this product, blamed on one occasion on "a need to improve the chip's speech-processing capabilities",<ref name="byte199501_ims">{{ cite magazine | url=https://archive.org/details/199501/page/n39/mode/1up | title=On-Line-Access Services Inconsistent for the Blind | magazine=Byte | last1=Lazzaro | first1=Joseph J. | date=January 1995 | access-date=12 June 2022 | pages=36 }}</ref> apparently led to the company seeking to introduce another chip, the [[Meta6000]], aiming to compete with Intel's P6 products.<ref name="byte199611_ims">{{ cite magazine | url=https://archive.org/details/eu_BYTE-1996-11_OCR/page/n135/mode/1up | title=IMS Rides Again With The Meta6000 | magazine=Byte | date=November 1996 | access-date=12 June 2022 | pages=90 }}</ref> Ultimately, IMS entered bankruptcy having sold patents to a litigator, TechSearch, who in 1998 attempted to sue Intel for infringement of an IMS patent.<ref name="electronicnews19980810_intel">{{ cite magazine | url=https://archive.org/details/sim_electronic-news_1998-08-10_44_2231/page/n23/mode/1up | title=Chip Law Firms Kept Busy | magazine=Electronic News | date=10 August 1998 | access-date=12 June 2022 | last1=Brown | first1=Peter | pages=24 }}</ref> TechSearch reportedly lost their case but sought to appeal, also seeking to sue Intel for "libel and slander" on the basis of comments made by an Intel representative who had characterised TechSearch's business model unfavourably in remarks to the press.<ref name="perelman">{{ cite book | url=https://archive.org/details/stealthisideaint0000pere/page/62/mode/2up | title=Steal This Idea: Intellectual Property Rights and the Corporate Confiscation of Creativity | publisher=Palgrave | last1=Perelman | first1=Michael | isbn=0-312-29408-5 | date=April 2002 | access-date=12 June 2022 | edition=1 | pages=62–63 }}</ref>

After the mainline 68000 processors' demise, the 68000 family has been used to some extent in [[microcontroller]] and embedded microprocessor versions. These chips include the ones listed under "other" above, i.e. the [[CPU32]] (aka [[Freescale 683XX|68330]]), the [[Freescale ColdFire|ColdFire]], the [[QUICC]] and the [[Freescale DragonBall|DragonBall]].

With the advent of [[Field Programmable Gate Array|FPGA]] technology an international team of hardware developers have re-created the [[68000]] with many enhancements as an FPGA core. Their core is known as the [[68080]] and is used in Vampire-branded Amiga accelerators.<ref>{{Cite web|url=http://www.apollo-core.com/|title=APOLLO 68080 - High Performance Processor|last=Boehn|first=Gunnar von|website=www.apollo-core.com|access-date=2017-09-29}}</ref>

[[Magnetic Scrolls]] used a subset of the 68000's instructions as a base for the virtual machine in their [[text adventures]].

==Competitors==

===Desktop===
During the 1980s and early 1990s, when the 68000 was widely used in desktop computers, it mainly competed against [[Intel]]'s [[x86]] architecture used in [[IBM PC compatible]]s. Generation 1 68000 CPUs competed against mainly the [[16-bit computing|16-bit]] [[Intel 8086|8086]], [[Intel 8088|8088]], and [[Intel 80286|80286]]. Generation 2 competed against the [[80386]] (the first 32-bit x86 processor), and generation 3 against the [[80486]]. The fourth generation competed with the [[P5 (microarchitecture)|P5]] [[Pentium]] line, but it was not nearly as widely used as its predecessors, since much of the old 68000 marketplace was either defunct or nearly so (as was the case with Atari and NeXT), or converting to newer architectures ([[PowerPC]] for the [[Mac (computer)|Macintosh]] and [[Amiga]], [[SPARC]] for [[Sun Microsystems|Sun]], and [[MIPS architecture|MIPS]] for [[Silicon Graphics]] (SGI)).

===Embedded===
{{Main|Microcontroller#Types}}

There are dozens of processor architectures that are successful in [[embedded system]]s. Some are microcontrollers which are much simpler, smaller, and cheaper than the 68000, while others are relatively sophisticated and can run complex software. Embedded versions of the 68000 often compete with processor architectures based on [[PowerPC]], [[ARM architecture|ARM]], [[MIPS architecture|MIPS]], [[SuperH]], and others.

==See also==
* [[VMEbus]], an external [[Computer_bus|computer bus standard]] designed for the 68000 series

==References==
{{Reflist}}

==Bibliography==
* Howe, Dennis, ed. (1983). ''Free On-Line Dictionary of Computing''. Imperial College, London. http://foldoc.org. Retrieved September 4, 2007.

==External links==
{{wikibooks|68000 Assembly}}
* [https://archive.org/stream/byte-magazine-1986-09/1986_09_BYTE_11-09_The_68000_Family#page/n171/mode/2up BYTE Magazine, September 1986: The 68000 Family]
* [http://oscomp.hu/bgafc/oses468k.php A quite an extensive list of operating systems supporting 680x0 processors]

{{Motorola processors}}

{{Authority control}}

[[Category:Instruction set architectures]]
[[Category:68k architecture]]
[[Category:68k microprocessors| ]]
[[Category:32-bit computers]]