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====[[Xeon]] (64-bit NetBurst)==== * '''Nocona''' ** Introduced 2004 * '''Irwindale''' ** Introduced 2004 * '''Cranford''' ** Introduced April 2005 ** MP version of Nocona * '''Potomac''' ** Introduced April 2005 ** Cranford with 8 MB of L3 cache * '''Paxville DP''' (2.8 GHz) ** Introduced October 10, 2005 ** Dual-core version of Irwindale, with 4 MB of L2 cache (2 MB per core) ** 2.8 GHz ** 800 MT/s front-side bus * '''Paxville MP''' β 90 nm process (2.67 β 3.0 GHz) ** Introduced November 1, 2005 ** Dual-core Xeon 7000 series ** MP-capable version of Paxville DP ** 2 MB of L2 cache (1 MB per core) or 4 MB of L2 (2 MB per core) ** 667 MT/s FSB or 800 MT/s FSB * '''Dempsey''' β 65 nm process (2.67β3.73 GHz) ** Introduced May 23, 2006 ** Dual-core Xeon 5000 series ** MP version of Presler ** 667 MT/s or 1066 MT/s FSB ** 4 MB of L2 cache (2 MB per core) ** [[LGA 771]] (Socket J). * '''Tulsa''' β 65 nm process (2.5β3.4 GHz) ** Introduced August 29, 2006 ** Dual-core Xeon 7100-series ** Improved version of Paxville MP ** 667 MT/s or 800 MT/s FSB
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