Editing X86 (section)

==Addressing modes==
[[Addressing mode]]s for 16-bit processor modes can be summarized by the formula:<ref>{{cite web|title=The 8086 Family User's Manual|page=2{{hyp}}68|date=October 1979|publisher=Intel Corporation|url=http://bitsavers.org/components/intel/8086/9800722-03_The_8086_Family_Users_Manual_Oct79.pdf|access-date=March 28, 2018|archive-date=April 4, 2018|archive-url=https://web.archive.org/web/20180404223644/http://www.bitsavers.org/components/intel/8086/9800722-03_The_8086_Family_Users_Manual_Oct79.pdf|url-status=live}}</ref><ref>{{cite web|title=iAPX 286 Programmer's Reference Manual|at=2.4.3 Memory Addressing Modes|year=1983|publisher=Intel Corporation|url=http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|access-date=August 28, 2017|archive-date=August 28, 2017|archive-url=https://web.archive.org/web/20170828232803/http://www.bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|url-status=live}}</ref>
:<math>
\begin{matrix}
  \mathtt{CS}: \\ \mathtt{DS}: \\ \mathtt{SS}: \\ \mathtt{ES}:
\end{matrix}\ \ 
\begin{pmatrix} \\
  \begin{bmatrix}
    \mathtt{BX} \\ \mathtt{BP}
  \end{bmatrix}
  +
  \begin{bmatrix}
    \mathtt{SI} \\ \mathtt{DI}
  \end{bmatrix} \\ \\
\end{pmatrix}
+
\rm displacement
</math>

Addressing modes for 32-bit x86 processor modes<ref>{{cite book|title=80386 Programmer's Reference Manual|at=2.5.3.2 EFFECTIVE-ADDRESS COMPUTATION|year=1986|publisher=Intel Corporation|url=http://bitsavers.org/components/intel/80386/230985-001_80386_Programmers_Reference_Manual_1986.pdf|access-date=March 28, 2018|archive-date=December 28, 2018|archive-url=https://web.archive.org/web/20181228110138/http://bitsavers.org/components/intel/80386/230985-001_80386_Programmers_Reference_Manual_1986.pdf|url-status=live}}</ref> can be summarized by the formula:<ref name="addrmodes">{{cite book|title=Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture|at=Chapter 3|date=March 2018|publisher=Intel Corporation|url=http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html|access-date=March 19, 2014|archive-date=January 26, 2012|archive-url=https://web.archive.org/web/20120126002939/http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html|url-status=live}}</ref>
:<math>
\begin{matrix}
  \mathtt{CS}: \\ \mathtt{DS}: \\ \mathtt{SS}: \\ \mathtt{ES}: \\ \mathtt{FS}: \\ \mathtt{GS}:
\end{matrix}\ \ 
\begin{bmatrix}
  \mathtt{EAX} \\ \mathtt{EBX} \\ \mathtt{ECX} \\ \mathtt{EDX} \\ \mathtt{ESP} \\ \mathtt{EBP} \\ \mathtt{ESI} \\ \mathtt{EDI}
\end{bmatrix}
+
\begin{pmatrix}\\
  \begin{bmatrix}
    \mathtt{EAX} \\ \mathtt{EBX} \\ \mathtt{ECX} \\ \mathtt{EDX} \\ \mathtt{EBP} \\ \mathtt{ESI} \\ \mathtt{EDI}
  \end{bmatrix}
  *
  \begin{bmatrix}
    1 \\ 2 \\ 4 \\ 8
  \end{bmatrix} \\ \\
\end{pmatrix}
+
\rm displacement
</math>

Addressing modes for the 64-bit processor mode can be summarized by the formula:<ref name="addrmodes"/>
:<math>
\begin{Bmatrix} \\
  \begin{matrix}
    \mathtt{FS}: \\ \mathtt{GS}:
  \end{matrix}\ \ 
  \begin{bmatrix}
    \vdots \\
    \mathtt{GPR} \\
    \vdots
  \end{bmatrix}
  +
  \begin{pmatrix} \\
    \begin{bmatrix}
      \vdots \\
      \mathtt{GPR} \\
      \vdots \\
    \end{bmatrix}
    *
    \begin{bmatrix}
      1\\2\\4\\8
    \end{bmatrix} \\ \\
  \end{pmatrix} \\ \\
  \hline \\
  \begin{matrix}
    \mathtt{RIP}
  \end{matrix} \\ \\
\end{Bmatrix}
+
\rm displacement
</math>

Instruction relative addressing in 64-bit code (RIP + displacement, where RIP is the [[instruction pointer|instruction pointer register]]) simplifies the implementation of [[position-independent code]] (as used in [[shared libraries]] in some operating systems).<ref name="Andriesse 2019">{{cite book | last=Andriesse | first=Dennis | title=Practical binary analysis: build your own Linux tools for binary instrumentation, analysis, and disassembly | publisher=No Starch Press, Inc | publication-place=San Francisco, CA | year=2019 | isbn=978-1-59327-913-4 | oclc=1050453850 | section=6.5 Effects of Compiler Settings on Disassembly}}</ref>

The 8086 had {{val|64|u=KB}} of eight-bit (or alternatively {{val|32|u=K-word of 16-bit}}) [[I/O]] space, and a {{val|64|u=KB}} (one segment) [[Stack (data structure)|stack]] in memory supported by [[computer hardware]]. Only words (two bytes) can be pushed to the stack. The stack grows toward numerically lower addresses, with {{mono|SS:SP}} pointing to the most recently pushed item. There are 256 [[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[Return statement|return address]].