Editing Verilog (section)

==Example==

A simple example of two [[Flip-flop (electronics)|flip-flops]] follows:
<syntaxhighlight lang="verilog">
module toplevel(clock,reset);
  input clock;
  input reset;

  reg flop1;
  reg flop2;

  always @ (posedge reset or posedge clock)
    if (reset)
      begin
        flop1 <= 0;
        flop2 <= 1;
      end
    else
      begin
        flop1 <= flop2;
        flop2 <= flop1;
      end
endmodule
</syntaxhighlight>

The <code><=</code> operator in Verilog is another aspect of its being a hardware description language as opposed to a normal procedural language. This is known as a "non-blocking" assignment. Its action does not register until after the always block has executed. This means that the order of the assignments is irrelevant and will produce the same result: flop1 and flop2 will swap values every clock.

The other assignment operator <code>=</code> is referred to as a blocking assignment. When <code>=</code> assignment is used, for the purposes of logic, the target variable is updated immediately. In the above example, had the statements used the <code>=</code> blocking operator instead of <code><=</code>, flop1 and flop2 would not have been swapped. Instead, as in traditional programming, the compiler would understand to simply set flop1 equal to flop2 (and subsequently ignore the redundant logic to set flop2 equal to flop1).

An example [[counter (digital)|counter]] circuit follows:
<syntaxhighlight lang="verilog">
module Div20x (rst, clk, cet, cep, count, tc);
// TITLE 'Divide-by-20 Counter with enables'
// enable CEP is a clock enable only
// enable CET is a clock enable and
// enables the TC output
// a counter using the Verilog language

parameter size = 5;
parameter length = 20;

input rst; // These inputs/outputs represent
input clk; // connections to the module.
input cet;
input cep;

output [size-1:0] count;
output tc;

reg [size-1:0] count; // Signals assigned
                      // within an always
                      // (or initial)block
                      // must be of type reg

wire tc; // Other signals are of type wire

// The always statement below is a parallel
// execution statement that
// executes any time the signals
// rst or clk transition from low to high

always @ (posedge clk or posedge rst)
  if (rst) // This causes reset of the cntr
    count <= {size{1'b0}};
  else
  if (cet && cep) // Enables both  true
    begin
      if (count == length-1)
        count <= {size{1'b0}};
      else
        count <= count + 1'b1;
    end

// the value of tc is continuously assigned
// the value of the expression
assign tc = (cet && (count == length-1));

endmodule
</syntaxhighlight>

An example of delays:
<syntaxhighlight lang="verilog">
...
reg a, b, c, d;
wire e;
...
always @(b or e)
  begin
    a = b & e;
    b = a | b;
    #5 c = b;
    d = #6 c ^ e;
  end
</syntaxhighlight>

The '''always''' clause above illustrates the other type of method of use, i.e. it executes whenever any of the entities in the list (the '''b''' or '''e''') changes. When one of these changes, '''a''' is immediately assigned a new value, and due to the blocking assignment, ''b'' is assigned a new value afterward (taking into account the new value of '''a'''). After a delay of 5 time units, '''c''' is assigned the value of '''b''' and the value of '''c ^ e''' is tucked away in an invisible store. Then after 6 more time units, '''d''' is assigned the value that was tucked away.

Signals that are driven from within a process (an initial or always block) must be of type '''reg'''. Signals that are driven from outside a process must be of type '''wire'''. The keyword '''reg''' does not necessarily imply a hardware register.