Editing VHDL (section)

===MUX template===
The [[multiplexer]], or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs <code>A</code> and <code>B</code>, selector <code>S</code> and output <code>X</code>. Note that there are many other ways to express the same MUX in VHDL.<ref>{{cite web |url=https://www.fpgatutorial.com/vhdl-logical-operators-and-signal-assignments-for-combinatorial-logic/#vhdl-mux |title=VHDL Logical Operators and Signal Assignments for Combinatorial Logic |website=FPGAtutorial |date=16 May 2020 |access-date=2020-08-23}}</ref>
<syntaxhighlight lang="VHDL">X <= A when S = '1' else B;</syntaxhighlight>

A more complex example of a MUX with 4×3 inputs and a 2-bit selector:
<syntaxhighlight lang="vhdl">
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
  port(
    a1      : in  std_logic_vector(2 downto 0);
    a2      : in  std_logic_vector(2 downto 0);
    a3      : in  std_logic_vector(2 downto 0);
    a4      : in  std_logic_vector(2 downto 0);
    sel     : in  std_logic_vector(1 downto 0);
    b       : out std_logic_vector(2 downto 0)
  );
end mux4;
architecture rtl of mux4 is
  -- declarative part: empty
begin
  p_mux : process(a1,a2,a3,a4,sel)
  begin
    case sel is
      when "00" => b <= a1 ;
      when "01" => b <= a2 ;
      when "10" => b <= a3 ;
      when others => b <= a4 ;
    end case;
  end process p_mux;
end rtl;
</syntaxhighlight>