Editing Semiconductor device fabrication (section)

===Front-end-of-line (FEOL) processing===
{{Main|FEOL}}

Wafer processing is separated into FEOL and BEOL stages. FEOL processing refers to the formation of the [[transistor]]s directly in the [[silicon]]. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through [[epitaxy]].<ref>{{Cite book|url=https://books.google.com/books?id=PsVVKz_hjBgC&dq=silicon+wafer+epitaxial+layer&pg=SA3-PA49|title=Handbook of Semiconductor Manufacturing Technology|first1=Yoshio|last1=Nishi|first2=Robert|last2=Doering|date=December 19, 2017|publisher=CRC Press|isbn=978-1-4200-1766-3 |via=Google Books}}</ref><ref>{{Cite book|url=https://books.google.com/books?id=VFMPEAAAQBAJ&dq=silicon+wafer+epitaxial+layer&pg=PA75|title=Microelectronic Materials|first=C. R. M.|last=Grovenor|date=October 5, 2017|publisher=Routledge|isbn=978-1-351-43154-5 |via=Google Books}}</ref>  In the most advanced [[logic device]]s, ''prior'' to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built.  One method involves introducing a ''straining step'' wherein a silicon variant such as [[silicon-germanium]] (SiGe) is deposited.  Once the epitaxial silicon is deposited, the [[crystal lattice]] becomes stretched somewhat, resulting in improved electronic mobility.  Another method, called ''[[silicon on insulator]]'' technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy.  This method results in the creation of transistors with reduced [[Parasitic element (electrical networks)|parasitic effects]]. Semiconductor equipment may have several chambers which process wafers in processes such as deposition and etching. Many pieces of equipment handle wafers between these chambers in an internal nitrogen or vacuum environment to improve process control.<ref name="auto4"/> Wet benches with tanks containing chemical solutions were historically used for cleaning and etching wafers.<ref>{{cite book | url=https://books.google.com/books?id=XdY7DQAAQBAJ&dq=semiconductor+wet+bench&pg=PA287 | isbn=978-981-310-671-0 | title=Semiconductor Manufacturing Technology | date=3 March 2008 | publisher=World Scientific Publishing Company }}</ref>

At the 90nm node, transistor channels made with strain engineering were introduced to improve drive current in PMOS transistors by introducing regions with Silicon-Germanium in the transistor. The same was done in NMOS transistors at the 20nm node.<ref name="auto9"/>

In 2007, HKMG (high-k/metal gate) transistors were introduced by Intel at the 45nm node, which replaced polysilicon gates which in turn replaced metal gate (aluminum gate)<ref>{{cite book | url=https://books.google.com/books?id=FezIEAAAQBAJ&dq=aluminum+gate+transistor&pg=PA102 | title=75th Anniversary of the Transistor | isbn=978-1-394-20244-7 | last1=Nathan | first1=Arokia | last2=Saha | first2=Samar K. | last3=Todi | first3=Ravi M. | date=August 2023 | publisher=John Wiley & Sons }}</ref> technology in the 1970s.<ref>{{Cite conference|url=https://ieeexplore.ieee.org/document/6212925|title=High-k/metal gates in leading edge silicon devices |conference=2012 SEMI Advanced Semiconductor Manufacturing Conference |doi=10.1109/ASMC.2012.6212925 |s2cid=32122636 }}</ref> High-k dielectric such as hafnium oxide (HfO<sub>2</sub>) replaced silicon oxynitride (SiON), in order to prevent large amounts of leakage current in the transistor while allowing for continued scaling or shrinking of the transistors. However HfO<sub>2</sub> is not compatible with polysilicon gates which requires the use of a metal gate. Two approaches were used in production: gate-first and gate-last. Gate-first consists of depositing the high-k dielectric and then the gate metal such as Tantalum nitride whose workfunction depends on whether the transistor is NMOS or PMOS, polysilicon deposition, gate line patterning, source and drain ion implantation, dopant anneal, and silicidation of the polysilicon and the source and drain.<ref>Robertson, J., & Wallace, R. M. (2015). High-K materials and metal gates for CMOS applications. Materials Science and Engineering: R: Reports, 88, 1–41. doi:10.1016/j.mser.2014.11.001</ref><ref>Frank, M. M. (2011). High-k / metal gate innovations enabling continued CMOS scaling. 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC). doi:10.1109/essderc.2011.6044239</ref> In DRAM memories this technology was first adopted in 2015.<ref>{{Cite conference|url=https://ieeexplore.ieee.org/document/7409775|title=Gate-first high-k/metal gate DRAM technology for low power and high performance products |conference=2015 IEEE International Electron Devices Meeting (IEDM) |doi=10.1109/IEDM.2015.7409775 |s2cid=35956689 }}</ref>

Gate-last consisted of first depositing the [[High-κ dielectric]], creating dummy gates, manufacturing sources and drains by ion deposition and dopant annealing, depositing an "interlevel dielectric (ILD)" and then polishing, and removing the dummy gates to replace them with a metal whose workfunction depended on whether the transistor was NMOS or PMOS, thus creating the metal gate. A third process, full silicidation (FUSI)<ref>{{Cite web|url=https://sst.semiconductor-digest.com/2010/03/integrating-high-k/|title=Integrating high-k /metal gates: gate-first or gate-last? &#124; Semiconductor Digest}}</ref> was not pursued due to manufacturing problems.<ref>{{Cite web|url=https://sst.semiconductor-digest.com/2009/12/hkmg_-gate-first_vs/|title=IEDM 2009: HKMG gate-first vs gate-last options &#124; Semiconductor Digest}}</ref> Gate-first became dominant at the 22nm/20nm node.<ref>{{cite web | url=https://www.eetimes.com/tracing-samsungs-road-to-14nm/ | title=Tracing Samsung's Road to 14nm | date=12 May 2015 }}</ref><ref>{{cite book | url=https://books.google.com/books?id=IXeQDwAAQBAJ&dq=hkmg+gate+last&pg=PA18 | isbn=978-1-78923-496-1 | title=Complementary Metal Oxide Semiconductor | date=August 2018 | publisher=BoD – Books on Demand }}</ref> HKMG has been extended from planar transistors for use in FinFET and nanosheet transistors.<ref>{{Cite web|url=https://semiengineering.com/whats-after-finfets/|title=What's After FinFETs?|first=Mark|last=LaPedus|date=July 24, 2017|website=Semiconductor Engineering}}</ref> Hafnium silicon
oxynitride can also be used instead of Hafnium oxide.<ref>{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/4154394|title=2006 International Electron Devices Meeting|doi=10.1109/IEDM.2006.346959 |s2cid=23881959 |chapter=High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates |date=2006 |last1=Tateshita |first1=Y. |last2=Wang |first2=J. |last3=Nagano |first3=K. |last4=Hirano |first4=T. |last5=Miyanami |first5=Y. |last6=Ikuta |first6=T. |last7=Kataoka |first7=T. |last8=Kikuchi |first8=Y. |last9=Yamaguchi |first9=S. |last10=Ando |first10=T. |last11=Tai |first11=K. |last12=Matsumoto |first12=R. |last13=Fujita |first13=S. |last14=Yamane |first14=C. |last15=Yamamoto |first15=R. |last16=Kanda |first16=S. |last17=Kugimiya |first17=K. |last18=Kimura |first18=T. |last19=Ohchi |first19=T. |last20=Yamamoto |first20=Y. |last21=Nagahama |first21=Y. |last22=Hagimoto |first22=Y. |last23=Wakabayashi |first23=H. |last24=Tagawa |first24=Y. |last25=Tsukamoto |first25=M. |last26=Iwamoto |first26=H. |last27=Saito |first27=M. |last28=Kadomura |first28=S. |last29=Nagashima |first29=N. |pages=1–4 |isbn=1-4244-0438-X }}</ref><ref>{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/4472451|title=2007 International Workshop on Physics of Semiconductor Devices|doi=10.1109/IWPSD.2007.4472451 |s2cid=25926459 |chapter=High-k/Metal Gates- from research to reality |date=2007 |last1=Narayanan |first1=V. |pages=42–45 |isbn=978-1-4244-1727-8 }}</ref><ref name="auto4"/><ref name="auto2">{{Cite web|url=https://spectrum.ieee.org/the-highk-solution|title=The High-k Solution - IEEE Spectrum|website=[[IEEE]]}}</ref><ref name="auto1">{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/4405765|title=2007 IEEE Custom Integrated Circuits Conference|doi=10.1109/CICC.2007.4405765 |s2cid=1589266 |chapter=High-K/Metal Gate Technology: A New Horizon |date=2007 |last1=Khare |first1=Mukesh |pages=417–420 |isbn=978-1-4244-0786-6 }}</ref> 

Since the 16nm/14nm node, Atomic layer etching (ALE) is increasingly used for etching as it offers higher precision than other etching methods. In production, plasma ALE is commonly used, which removes materials unidirectionally, creating structures with vertical walls. Thermal ALE can also be used to remove materials isotropically, in all directions at the same time but without the capability to create vertical walls. Plasma ALE was initially adopted for etching contacts in transistors, and since the 7nm node it is also used to create transistor structures by etching them.<ref name="auto8"/>

====Gate oxide and implants====
{{Main| self-aligned gate | doping (semiconductor) }}
Front-end surface engineering is followed by growth of the [[gate dielectric]] (traditionally [[silicon dioxide]]), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In [[dynamic random-access memory]] (DRAM) devices, storage [[capacitors]] are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer [[Qimonda]] implemented these capacitors with trenches etched deep into the silicon surface).