Editing NCUBE (section)

===nCUBE-3===
The '''nCUBE-3''' CPU used a 64-bit [[arithmetic logic unit]] (ALU). Its improvements included a process-shrink to 0.5u, allowing the speed to be increased to 50&nbsp;MHz (with plans for 66 and 100&nbsp;MHz). The CPU was also [[superscalar]] and included 16&nbsp;KB instruction and data [[CPU cache|caches]], and a [[memory management unit]] for virtual memory support.

Additional I/O links were added, with 2 dedicated to I/O and 16 for interconnects, allowing for up to 65,536 CPUs in the hypercube. The channels operated at 100&nbsp;Mbit/s, due to use of 2-bit parallel lines, instead of the serial lines used previously. The nCUBE-3 also added [[Fault tolerance|fault-tolerant]] adaptive routing support, in addition to fixed routing, although in retrospect it's not entirely clear why.

A fully loaded nCUBE-3 machine can use up to 65,536 processors, for 3 million MIPS and 6.5 teraFLOPS; the maximum memory would be 65&nbsp;TB, with a network I/O capability of 24&nbsp;TB/second.<ref>{{cite book|last1=Duzett|first1=B|last2=Buck|first2=R|title=&#91;Proceedings 1992&#93; the Fourth Symposium on the Frontiers of Massively Parallel Computation|chapter=An overview of the nCUBE 3 supercomputer|date=19–21 Oct 1992|volume=[Proceedings 1992]|pages=458–464|doi=10.1109/FMPC.1992.234880|isbn=978-0-8186-2772-9|s2cid=58781077}}</ref> Thus, the processor is biased in terms of I/O, which is usually the limitation. The nChannel board provides 16 I/O channels, where each channel can support transfers at 20&nbsp;MB/s.

A [[microkernel]] was developed for the nCUBE-3 machine, but it was never completed, having been abandoned in favor of [[Plan 9 from Bell Labs|Plan 9]]'s Transit operating system.