Editing Intel 8008 (section)

==Designers==
*'''CTC''' (''Instruction set and architecture''): [[Victor Poor]] and [[Harry Pyle]].
*'''Intel''' (''Implementation in silicon''):
** [[Marcian Hoff|Ted Hoff]] and [[Stanley Mazor|Stan Mazor]] proposed a single-chip implementation of the CTC architecture, using RAM-register memory rather than shift-register memory, and also added a few instructions and interrupt facility. The 8008 (originally called 1201) chip design started before the 4004 development. Hoff and Mazor, however, could not and did not develop a "silicon design" because they were neither chip designers nor process developers, and furthermore the necessary [[bootstrap load]] silicon-gate-based design methodology and circuits, under development by Federico Faggin for the 4004, were not yet available.<ref>{{cite journal |author-last1=Faggin |author-first1=Federico |author-link1=Federico Faggin |author-last2=Hoff, Jr. |author-first2=Marcian E. |author-link2=Marcian Hoff |author-last3=Mazor |author-first3=Stanley |author-link3=Stanley Mazor |author-last4=Shima |author-first4=Masatoshi |author-link4=Masatoshi Shima |title=The History of the 4004 |journal=IEEE Micro |volume=16 |issue=6 |pages=10–19 |publisher=IEEE Computer Society |location=Los Alamitos, USA |date=December 1996 |issn=0272-1732 |doi=10.1109/40.546561}}</ref><!-- also dubious; neither Hoff nor Mazor were process designers, but Hoff developed dynamic ram, so he could be a chip designer. Hoff, Mazor, and a process engineer (who was not Faggin) were responsible for NPULS (SPICE-like) circuit models and circuit simulations. Mazor was running architecture simulations. -->
** [[Federico Faggin]], having finished the design of the 4004, became leader of the project from January 1971 until its successful completion in April 1972, after it had been suspended – for lack of progress – for about seven months. 
** [[Hal Feeney]], project engineer, did the detailed logic design, circuit design, and physical layout under Faggin's supervision, employing the same design methodology that Faggin had originally developed for the Intel 4004 microprocessor, and utilizing the basic circuits he had developed for the 4004. A combined "HF" logo was etched onto the chip about halfway between the D5 and D6 bonding pads.<!-- Need an image for this claim |date=October 2017 -->