Editing IBM 1620 (section)

==Model I==
[[Image:1620 Model I Layout.png|thumb|Drawing showing internal layout of "gates"]]
The '''IBM 1620 Model I''' (commonly called "1620" from 1959 until the 1962 introduction of the [[#Model II|Model II]]) was the original. It was produced as inexpensively as possible, to [[#Under $1620|keep the price low]].
* [[#CADET|It lacked]] conventional [[arithmetic logic unit|ALU]] hardware: arithmetic was done by [[core memory|memory table]] lookup. Addition and subtraction used a 100-digit table (at address 00300..00399). Multiplication used a 200-digit table (at address 00100..00299).<ref name=FP.CE>{{cite book  |title=227-5630-1 IBM 1620 Floating Point Feature CE Manual
|url=http://bitsavers.trailing-edge.com/pdf/ibm/1620/fe/227-5630-1_IBM_1620_Floating_Point_Feature_CE_Manual_1962.pdf |archive-url=https://ghostarchive.org/archive/20221010/http://bitsavers.trailing-edge.com/pdf/ibm/1620/fe/227-5630-1_IBM_1620_Floating_Point_Feature_CE_Manual_1962.pdf |archive-date=2022-10-10 |url-status=live
|publisher=IBM Corporation}}</ref>{{rp|p.4.4}} The basic machine used software subroutines for division, although optional divide hardware could be installed that used a repeated subtraction algorithm. Floating-point arithmetic instructions were an available option (if the divide option was installed).
* The first 20,000 decimal digits of [[magnetic-core memory]] were internal to the [[central processing unit|CPU]] itself (which reduced the floor space requirements of the basic system). Expansion to either 40,000 or 60,000 decimal digits required the addition of an IBM 1623 Memory unit. The memory cycle time was 20&nbsp;[[microsecond|μs]] (that is, the memory speed was 50&nbsp;[[kilohertz|kHz]] = 1/20 of a MHz). A Memory Address Register Storage (MARS)<ref name=FP.CE/> Core memory read, clear, or write operation took 2&nbsp;μs and each write operation was automatically (but not necessarily immediately) preceded by a read or clear operation of the same "register(s)" during the 20&nbsp;μs memory cycle.
* The central processor clock speed was 1&nbsp;[[megahertz|MHz]], which was divided by 20 by a 10-position [[ring counter]] to provide the system timing and control signals. Instructions took eight memory cycles (160&nbsp;μs) to fetch and a variable number of memory cycles to execute. Indirect addressing<ref name=IBM.intro59/> added four memory cycles (80&nbsp;μs) for each level of indirection.
* It weighed about {{convert|1210|lb|kg}}.<ref>{{Cite web
  |url=https://www.ed-thelen.org/comp-hist/BRL61-ibm1401.html#IBM-1620
  |title=IBM 1620|last=Weik|first=Martin H.|date=Mar 1961
  |website=ed-thelen.org |series=A Third Survey of Domestic Electronic Digital Computing Systems
  }}</ref>