Editing GE 645 (section)

=== Address base registers ===
The GE 645 had 8 Address Base Registers (abr's),<ref>Organick (1972), ''op. cit., p.'' 18</ref> these could operate in either "paired" or "unpaired" modes.<ref name="Green">{{cite web |last1=Green |first1=Paul |title=Multics Virtual Memory - Tutorial and Reflections |url=https://multicians.org/pg/mvm.html |website=multicians.org |access-date=20 December 2023}}</ref> The later Honeywell 6180 changed these to 8 pointer registers. Each abr was 24-bits wide consisting of 18 bits for an address and 6 bits for control functions.<ref name=abr>Organick (1972), ''op. cit., p.'' 19</ref>

One bit of the control functions field indicates where an abr is "internal" or "external".  If an abr is internal, another 3-bit subfield of the control functions field specifies another abr with which this abr is paired; that other abr is external, with the external abr containing a segment number in the address field and the internal abr containing an offset within the segment specified by the external abr.<ref name="AH82-00" />{{rp|4{{hyp}}4}}  If an instruction or an indirect word refers to an external abr, the address field in the instruction or indirect word is used as an offset in the segment specified by the external abr.  If it refers to an internal abr, the address field in the instruction or indirect word is added to the offset in the abr, and the resulting value is used as an offset in the segment specified by the external abr with which the internal abr is paired.<ref name="AH82-00" />{{rp|6{{hyp}}26}}

The registers have the following formats depending on how bit 21 is set.<ref name="abr" />

Format as an "external" base, with bit 21 set:

<pre>
                         1 1 2 2 22 
        0                7 8 0 1 23 
       +------------------+---+-+--+
       |     PDW          |\\\|1|\\|
       +------------------+---+-+--+
</pre>

Format as a component to the effective "internal" address with a pointer to an "external" base, with bit 21 clear:

<pre>
                         1 1 2 2 22 
        0                7 8 0 1 23 
       +------------------+---+-+--+
       |     PY           |PB |0|\\|
       +------------------+---+-+--+
                                         
</pre>
* '''PDW''' is the Pointer to a descriptor word 
* '''PY''' is the component P of the effective internal address 'Y'
* '''PB''' is pointer to another base register whose bit 21 = 1


In Multics, an even-numbered abr and the following odd-numbered abr were paired. When writing in Assembly (EPLBSA/ALM)<ref group=NB>EPL BootStrap Assember / Assembly Language for Multics</ref> the standard Multics practice was to label these registers as follows:<ref>Organick (1972), ''op. cit., p.'' 20-21</ref>
* '''ap''' for abr 0
* '''ab''' for abr 1
* '''bp''' for abr 2
* '''bb''' for abr 3
* '''lp''' for abr 4
* '''lb''' for abr 5
* '''sp''' for abr 6
* '''sb''' for abr 7

The naming scheme is based around the following:<ref>Organick (1972), ''op. cit., p.'' 22-23</ref>
* '''a''' for argument-list pointer
* '''b''' for general base
* '''l''' for linkage-segment pointer
* '''s''' for stack-segment pointer

The 8 pointer registers in the Honeywell 6180 and its successors served the same purpose as the 4 paired base registers in the GE-645, referring to an offset within a segment.