Editing CMOS (section)

=== Static dissipation ===

Both NMOS and PMOS transistors have a gate–source [[threshold voltage]] (V<sub>th</sub>), below which the current (called ''sub threshold'' current) through the device will drop exponentially. Historically, CMOS circuits operated at supply voltages much larger than their threshold voltages (V<sub>dd</sub> might have been 5&nbsp;V, and V<sub>th</sub> for both NMOS and PMOS might have been 700&nbsp;mV). A special type of the transistor used in some CMOS circuits is the [[native transistor]], with near zero [[threshold voltage]].

SiO<sub>2</sub> is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130&nbsp;nm technology with gate oxides of 20&nbsp;Å or thinner.

Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily. Furthermore, recent studies have shown that leakage power reduces due to aging effects as a trade-off for devices to become slower.<ref>{{cite book |first1=A.L.H. |last1=Martínez |first2=S. |last2=Khursheed |first3=D. |last3=Rossi |chapter=Leveraging CMOS Aging for Efficient Microelectronics Design |title=2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS) |publisher= |year=2020 |isbn= 978-1-7281-8187-5|pages=1–4 |doi=10.1109/IOLTS50870.2020.9159742|s2cid=225582202 }}</ref>

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a V<sub>th</sub> of 200&nbsp;mV has a significant [[subthreshold leakage]] current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. [[Multi-threshold CMOS]] (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high V<sub>th</sub> transistors are used when switching speed is not critical, while low V<sub>th</sub> transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional [[Leakage (electronics)|leakage]] component because of current [[Quantum tunnelling|tunnelling]] through the extremely thin gate dielectric. Using [[high-κ dielectric]]s instead of [[silicon dioxide]] that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.<ref>A good overview of leakage and reduction methods are explained in the book [https://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-25737-2 Leakage in Nanometer CMOS Technologies] {{webarchive|url=https://web.archive.org/web/20111202012235/http://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-25737-2 |date=2011-12-02 }} {{ISBN|0-387-25737-3}}.</ref>