Editing X86 (section)

==Current implementations==
During [[Execution (computers)|execution]], current x86 processors employ a few extra decoding steps to split most instructions into smaller pieces called micro-operations. These are then handed to a [[control unit]] that buffers and schedules them in compliance with x86-semantics so that they can be executed, partly in parallel, by one of several (more or less specialized) [[execution units]]. These modern x86 designs are thus [[Instruction pipelining|pipelined]], [[superscalar]], and also capable of [[out-of-order execution|out of order]] and [[speculative execution]] (via [[branch prediction]], [[register renaming]], and [[memory dependence prediction]]), which means they may execute multiple (partial or complete) x86 instructions simultaneously, and not necessarily in the same order as given in the instruction stream.<ref>{{cite web|url=http://www.intel.com/support/processors/sb/CS-030169.htm?wapkw=8086+processor|title=Processors — What mode of addressing do the Intel Processors use?|access-date=September 14, 2014|archive-date=September 11, 2014|archive-url=https://web.archive.org/web/20140911003022/http://www.intel.com/support/processors/sb/CS-030169.htm?wapkw=8086+processor|url-status=live}}</ref>
Some Intel CPUs ([[Xeon#Foster|Xeon Foster MP]], some [[Pentium 4]], and some [[Nehalem (microarchitecture)|Nehalem]] and later [[Intel Core]] processors) and AMD CPUs (starting from [[Zen (microarchitecture)|Zen]]) are also capable of [[simultaneous multithreading]] with two [[thread (computer science)|threads]] per [[multi-core processor|core]] ([[Xeon Phi]] has four threads per core). Some Intel CPUs support [[transactional memory]] ([[Transactional Synchronization Extensions|TSX]]).

When introduced, in the mid-1990s, this method was sometimes referred to as a "RISC core" or as "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions. However, traditional [[microcode]] (used since the 1950s) also inherently shares many of the same properties; the new method differs mainly in that the translation to micro-operations now occurs asynchronously. Not having to synchronize the execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit.

The latest processors also do the opposite when appropriate; they combine certain x86 sequences (such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with fewer machine resources involved.

Another way to try to improve performance is to cache the decoded micro-operations, so the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again. Intel followed this approach with the Execution Trace Cache feature in their [[NetBurst]] microarchitecture (for Pentium 4 processors) and later in the Decoded Stream Buffer (for Core-branded processors since Sandy Bridge).<ref>{{cite web|url=http://software.intel.com/sites/products/documentation/doclib/iss/2013/amplifier/lin/ug_docs/GUID-143D1B76-D97F-454F-9B4B-91F2D791B66D.htm|title=DSB Switches|work=Intel VTune Amplifier 2013|publisher=Intel|access-date=August 26, 2013|archive-date=December 2, 2013|archive-url=https://web.archive.org/web/20131202232818/http://software.intel.com/sites/products/documentation/doclib/iss/2013/amplifier/lin/ug_docs/GUID-143D1B76-D97F-454F-9B4B-91F2D791B66D.htm|url-status=live}}</ref>

[[Transmeta]] used a completely different method in their [[Transmeta Crusoe|Crusoe]] x86 compatible CPUs. They used [[Just-in-time compilation|just-in-time]] translation to convert x86 instructions to the CPU's native [[VLIW]] instruction set. Transmeta argued that their approach allows for more power efficient designs since the CPU can forgo the complicated decode step of more traditional x86 implementations.