Editing Semiconductor device fabrication (section)

==Processing==
{{See also|Wafer fabrication}}
In semiconductor device fabrication, the various processing steps fall into four general categories:  deposition, removal, patterning, and modification of electrical properties.
* ''Deposition'' is any process that grows, coats, or otherwise transfers a material onto the wafer.  Available technologies include [[physical vapor deposition]] (PVD), [[chemical vapor deposition]] (CVD), [[Electroplating|electrochemical deposition]] (ECD), [[molecular beam epitaxy]] (MBE), and more recently, [[atomic layer deposition]] (ALD) among others. Deposition can be understood to include [[oxide]] layer formation, by [[thermal oxidation]] or, more specifically, [[LOCOS]].
* ''Removal'' is any process that removes material from the wafer; examples include etch processes (either [[Etching (microfabrication)#Wet etching|wet]] or [[Etching (microfabrication)#Plasma etching|dry]]) and [[chemical-mechanical planarization]] (CMP).
* ''Patterning'' is the shaping or altering of deposited materials, and is generally referred to as [[Photolithography|lithography]]. For example, in conventional lithography, the wafer is coated with a chemical called a ''[[photoresist]]''; then, a machine called an aligner or ''[[stepper]]'' focuses a [[photomask|mask]] image on the wafer using short-wavelength light; the exposed regions (for "positive" resist) are washed away by a developer solution. The wafer then undergoes etching where materials not protected by the mask are removed. After removal or other processing, the remaining photoresist is removed by "dry" stripping/[[plasma ashing]]/resist ashing or by "wet" resist stripper chemistry.<ref>{{Cite web|url=https://www.eesemi.com/wafer-cleaning.htm|title=Wafer Cleaning Procedures; Photoresist or Resist Stripping; Removal of Films and Particulates|website=www.eesemi.com|access-date=2020-10-14|archive-date=2020-10-15|archive-url=https://web.archive.org/web/20201015035229/https://www.eesemi.com/wafer-cleaning.htm|url-status=live}}</ref> Wet etching was widely used in the 1960s and 1970s,<ref>{{Cite book|url=https://books.google.com/books?id=tUJLAea0SMoC&dq=wet+etching+dry+etching&pg=PA1|title=Plasma Etching: Fundamentals and Applications|first=M.|last=Sugawara|date=May 28, 1998|publisher=OUP Oxford|isbn=978-0-19-159029-0 |via=Google Books}}</ref><ref>{{Cite book|url=https://books.google.com/books?id=eEYVBQAAQBAJ|title=Dry Etching Technology for Semiconductors|first=Kazuo|last=Nojiri|date=October 25, 2014|publisher=Springer|isbn=978-3-319-10295-5 |via=Google Books}}</ref> but it was replaced by dry etching/plasma etching starting at the 10 micron to 3 micron nodes.<ref>{{Cite book|url=https://books.google.com/books?id=tUJLAea0SMoC&q=Undercutting&pg=PA1|title=Plasma Etching: Fundamentals and Applications|first=M.|last=Sugawara|date=May 28, 1998|publisher=OUP Oxford|isbn=978-0-19-159029-0 |via=Google Books}}</ref><ref>{{Cite book|url=https://books.google.com/books?id=Smn6DwAAQBAJ&dq=wet+etching+dry+etching&pg=PA158|title=III-Nitrides Light Emitting Diodes: Technology and Applications|first1=Jinmin|last1=Li|first2=Junxi|last2=Wang|first3=Xiaoyan|last3=Yi|first4=Zhiqiang|last4=Liu|first5=Tongbo|last5=Wei|first6=Jianchang|last6=Yan|first7=Bin|last7=Xue|date=August 31, 2020|publisher=Springer Nature|isbn=978-981-15-7949-3 |via=Google Books}}</ref> This is because wet etching makes undercuts (etching under mask layers or resist layers with patterns).<ref>{{Cite book|url=https://books.google.com/books?id=uZ07AAAAQBAJ&q=Undercutting|title=Dry Etching for Microelectronics|first=R. A.|last=Powell|date=December 2, 2012|publisher=Elsevier|isbn=978-0-08-098358-5 |via=Google Books}}</ref><ref>{{Cite book|url=https://books.google.com/books?id=zAjYDwAAQBAJ&dq=wet+etching+dry+etching&pg=PA48|title=Fundamentals of Layout Design for Electronic Circuits|first1=Jens|last1=Lienig|first2=Juergen|last2=Scheible|date=March 19, 2020|publisher=Springer Nature|isbn=978-3-030-39284-0 |via=Google Books}}</ref><ref>{{Cite book|url=https://books.google.com/books?id=soHlnnTJ-qkC&q=Undercutting|title=Etching in Microsystem Technology|first=Michael|last=Köhler|date=July 11, 2008|publisher=John Wiley & Sons|isbn=978-3-527-61379-3 |via=Google Books}}</ref> Dry etching has become the dominant etching technique.<ref>{{Cite web|url=https://semiengineering.com/highly-selective-etch-rolls-out-for-next-gen-chips/|title=Highly Selective Etch Rolls Out For Next-Gen Chips|first=Mark|last=LaPedus|date=March 21, 2022|website=Semiconductor Engineering}}</ref>
* ''Modification of electrical properties'' has historically entailed [[Semiconductor doping|doping]] transistor ''sources'' and ''drains'' and polysilicon. Doping consists of introducing impurities into the atomic structure of a semiconductor material, in order to modify its electrical properties. Initially thermal diffusion with furnaces at 900-1200°C with gases containing dopants were used for doping wafers<ref>{{cite book | url=https://books.google.com/books?id=TzL5aUslKDUC&dq=thermal+diffusion+doping&pg=PA157 | title=Introduction to Microfabrication | isbn=978-0-470-02056-2 | last1=Franssila | first1=Sami | date=28 January 2005 | publisher=John Wiley & Sons }}</ref><ref>{{cite web | url=https://www.computerhistory.org/siliconengine/diffusion-process-developed-for-transistors/ | title=1954: Diffusion Process Developed for Transistors &#124; the Silicon Engine &#124; Computer History Museum }}</ref><ref>{{cite book | url=https://books.google.com/books?id=aoGUEAAAQBAJ&dq=thermal+diffusion+doping&pg=PA245 | title=Semiconductor Microchips and Fabrication: A Practical Guide to Theory and Manufacturing | isbn=978-1-119-86780-7 | last1=Lian | first1=Yaguang | date=10 October 2022 | publisher=John Wiley & Sons }}</ref> and there was resistance against [[ion implantation]] as it still required a separate furnace<ref>{{cite conference |url=https://www.axcelis.com/wp-content/uploads/2019/03/Major-Innovations-in-Beamline-Design.pdf |title=Review of Major Innovations in Beam Line Design |first1=Hilton |last1=Glavish |first2=Marvin |last2=Farley |conference=2018 22nd International Conference on Ion Implantation Technology (IIT) |doi=10.1109/IIT.2018.8807986}}</ref> but ion implantation ultimately prevailed in the 1970s<ref>{{cite journal |url=http://www.eelab.usyd.edu.au/ELEC5402/UserFiles/File/Lecture-Material-Others/MOS-History.pdf |title=History of Some Early Developments in Ion-Implantation Technology Leading to Silicon Transistor Manufacturing |first=Richard B. |last=Fair |journal=Proceedings of the IEEE |volume=86 |issue=1 |date=January 1998 |pages=111–137 |doi=10.1109/5.658764 |archive-url=https://web.archive.org/web/20070902023701/http://www.eelab.usyd.edu.au/ELEC5402/UserFiles/File/Lecture-Material-Others/MOS-History.pdf |archive-date=2 September 2007 |url-status=dead |access-date=26 February 2024 }}</ref> as it offers better reproducibility of results during manufacturing of chips,<ref name="ion-implantation-in-silicon-technology" /> however diffusion is still used for manufacturing silicon photovoltaic cells.<ref>{{cite journal |last1=Saga |first1=Tatsuo |title=Advances in crystalline silicon solar cell technology for industrial mass production |journal=NPG Asia Materials |date=July 2010 |volume=2 |issue=3 |pages=96–102 |doi=10.1038/asiamat.2010.82 }}</ref> Ion implantation is practical because of the high sensitivity of semiconductor devices to foreign atoms, as ion implantation does not deposit large numbers of atoms.<ref name="ion-implantation-in-silicon-technology" /> Doping processes with ion implantation are followed by [[furnace anneal]]ing<ref>{{cite book | chapter-url=https://link.springer.com/chapter/10.1007/978-3-540-45298-0_15 | doi=10.1007/978-3-540-45298-0_15 | chapter=Ion implantation in CMOS Technology: Machine Challenges | title=Ion Implantation and Synthesis of Materials | date=2006 | pages=213–238 | publisher=Springer | isbn=978-3-540-23674-0 }}</ref><ref name="ion-implantation-in-silicon-technology" /> or, in advanced devices, by [[rapid thermal anneal]]ing (RTA) to activate the dopants. Annealing was initially done at 500 to 700°C, but this was later increased to 900 to 1100°C. Implanters can either process a single wafer at a time or several, up to 17, mounted on a rotating disk.<ref name="ion-implantation-in-silicon-technology" />

Modification of electrical properties now also extends to the reduction of a material's [[dielectric constant]] in [[low-κ dielectric|low-κ insulators]] via exposure to [[ultraviolet light]] in UV processing (UVP). Modification is frequently achieved by [[oxidation]], which can be carried out to create semiconductor-insulator junctions, such as in the local oxidation of [[silicon]] ([[LOCOS]]) to fabricate [[MOSFET|metal oxide field effect transistors]]. Modern chips have up to eleven or more metal levels produced in over 300 or more sequenced processing steps. 

A recipe in semiconductor manufacturing is a list of conditions under which a wafer will be processed by a particular machine in a processing step during manufacturing.<ref>{{cite conference | url=https://ieeexplore.ieee.org/document/1716835 | title=Virtual Metrology Technique for Semiconductor Manufacturing |conference=The 2006 IEEE International Joint Conference on Neural Network Proceedings | doi=10.1109/IJCNN.2006.247284 | s2cid=1194426 }}</ref> Process variability is a challenge in semiconductor processing, in which wafers are not processed evenly or the quality or effectiveness of processes carried out on a wafer are not even across the wafer surface.<ref>{{Cite web|url=https://spectrum.ieee.org/the-threat-of-semiconductor-variability|title=The Threat of Semiconductor Variability - IEEE Spectrum|website=[[IEEE]]}}</ref>

===Front-end-of-line (FEOL) processing===
{{Main|FEOL}}

Wafer processing is separated into FEOL and BEOL stages. FEOL processing refers to the formation of the [[transistor]]s directly in the [[silicon]]. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through [[epitaxy]].<ref>{{Cite book|url=https://books.google.com/books?id=PsVVKz_hjBgC&dq=silicon+wafer+epitaxial+layer&pg=SA3-PA49|title=Handbook of Semiconductor Manufacturing Technology|first1=Yoshio|last1=Nishi|first2=Robert|last2=Doering|date=December 19, 2017|publisher=CRC Press|isbn=978-1-4200-1766-3 |via=Google Books}}</ref><ref>{{Cite book|url=https://books.google.com/books?id=VFMPEAAAQBAJ&dq=silicon+wafer+epitaxial+layer&pg=PA75|title=Microelectronic Materials|first=C. R. M.|last=Grovenor|date=October 5, 2017|publisher=Routledge|isbn=978-1-351-43154-5 |via=Google Books}}</ref>  In the most advanced [[logic device]]s, ''prior'' to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built.  One method involves introducing a ''straining step'' wherein a silicon variant such as [[silicon-germanium]] (SiGe) is deposited.  Once the epitaxial silicon is deposited, the [[crystal lattice]] becomes stretched somewhat, resulting in improved electronic mobility.  Another method, called ''[[silicon on insulator]]'' technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy.  This method results in the creation of transistors with reduced [[Parasitic element (electrical networks)|parasitic effects]]. Semiconductor equipment may have several chambers which process wafers in processes such as deposition and etching. Many pieces of equipment handle wafers between these chambers in an internal nitrogen or vacuum environment to improve process control.<ref name="auto4"/> Wet benches with tanks containing chemical solutions were historically used for cleaning and etching wafers.<ref>{{cite book | url=https://books.google.com/books?id=XdY7DQAAQBAJ&dq=semiconductor+wet+bench&pg=PA287 | isbn=978-981-310-671-0 | title=Semiconductor Manufacturing Technology | date=3 March 2008 | publisher=World Scientific Publishing Company }}</ref>

At the 90nm node, transistor channels made with strain engineering were introduced to improve drive current in PMOS transistors by introducing regions with Silicon-Germanium in the transistor. The same was done in NMOS transistors at the 20nm node.<ref name="auto9"/>

In 2007, HKMG (high-k/metal gate) transistors were introduced by Intel at the 45nm node, which replaced polysilicon gates which in turn replaced metal gate (aluminum gate)<ref>{{cite book | url=https://books.google.com/books?id=FezIEAAAQBAJ&dq=aluminum+gate+transistor&pg=PA102 | title=75th Anniversary of the Transistor | isbn=978-1-394-20244-7 | last1=Nathan | first1=Arokia | last2=Saha | first2=Samar K. | last3=Todi | first3=Ravi M. | date=August 2023 | publisher=John Wiley & Sons }}</ref> technology in the 1970s.<ref>{{Cite conference|url=https://ieeexplore.ieee.org/document/6212925|title=High-k/metal gates in leading edge silicon devices |conference=2012 SEMI Advanced Semiconductor Manufacturing Conference |doi=10.1109/ASMC.2012.6212925 |s2cid=32122636 }}</ref> High-k dielectric such as hafnium oxide (HfO<sub>2</sub>) replaced silicon oxynitride (SiON), in order to prevent large amounts of leakage current in the transistor while allowing for continued scaling or shrinking of the transistors. However HfO<sub>2</sub> is not compatible with polysilicon gates which requires the use of a metal gate. Two approaches were used in production: gate-first and gate-last. Gate-first consists of depositing the high-k dielectric and then the gate metal such as Tantalum nitride whose workfunction depends on whether the transistor is NMOS or PMOS, polysilicon deposition, gate line patterning, source and drain ion implantation, dopant anneal, and silicidation of the polysilicon and the source and drain.<ref>Robertson, J., & Wallace, R. M. (2015). High-K materials and metal gates for CMOS applications. Materials Science and Engineering: R: Reports, 88, 1–41. doi:10.1016/j.mser.2014.11.001</ref><ref>Frank, M. M. (2011). High-k / metal gate innovations enabling continued CMOS scaling. 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC). doi:10.1109/essderc.2011.6044239</ref> In DRAM memories this technology was first adopted in 2015.<ref>{{Cite conference|url=https://ieeexplore.ieee.org/document/7409775|title=Gate-first high-k/metal gate DRAM technology for low power and high performance products |conference=2015 IEEE International Electron Devices Meeting (IEDM) |doi=10.1109/IEDM.2015.7409775 |s2cid=35956689 }}</ref>

Gate-last consisted of first depositing the [[High-κ dielectric]], creating dummy gates, manufacturing sources and drains by ion deposition and dopant annealing, depositing an "interlevel dielectric (ILD)" and then polishing, and removing the dummy gates to replace them with a metal whose workfunction depended on whether the transistor was NMOS or PMOS, thus creating the metal gate. A third process, full silicidation (FUSI)<ref>{{Cite web|url=https://sst.semiconductor-digest.com/2010/03/integrating-high-k/|title=Integrating high-k /metal gates: gate-first or gate-last? &#124; Semiconductor Digest}}</ref> was not pursued due to manufacturing problems.<ref>{{Cite web|url=https://sst.semiconductor-digest.com/2009/12/hkmg_-gate-first_vs/|title=IEDM 2009: HKMG gate-first vs gate-last options &#124; Semiconductor Digest}}</ref> Gate-first became dominant at the 22nm/20nm node.<ref>{{cite web | url=https://www.eetimes.com/tracing-samsungs-road-to-14nm/ | title=Tracing Samsung's Road to 14nm | date=12 May 2015 }}</ref><ref>{{cite book | url=https://books.google.com/books?id=IXeQDwAAQBAJ&dq=hkmg+gate+last&pg=PA18 | isbn=978-1-78923-496-1 | title=Complementary Metal Oxide Semiconductor | date=August 2018 | publisher=BoD – Books on Demand }}</ref> HKMG has been extended from planar transistors for use in FinFET and nanosheet transistors.<ref>{{Cite web|url=https://semiengineering.com/whats-after-finfets/|title=What's After FinFETs?|first=Mark|last=LaPedus|date=July 24, 2017|website=Semiconductor Engineering}}</ref> Hafnium silicon
oxynitride can also be used instead of Hafnium oxide.<ref>{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/4154394|title=2006 International Electron Devices Meeting|doi=10.1109/IEDM.2006.346959 |s2cid=23881959 |chapter=High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates |date=2006 |last1=Tateshita |first1=Y. |last2=Wang |first2=J. |last3=Nagano |first3=K. |last4=Hirano |first4=T. |last5=Miyanami |first5=Y. |last6=Ikuta |first6=T. |last7=Kataoka |first7=T. |last8=Kikuchi |first8=Y. |last9=Yamaguchi |first9=S. |last10=Ando |first10=T. |last11=Tai |first11=K. |last12=Matsumoto |first12=R. |last13=Fujita |first13=S. |last14=Yamane |first14=C. |last15=Yamamoto |first15=R. |last16=Kanda |first16=S. |last17=Kugimiya |first17=K. |last18=Kimura |first18=T. |last19=Ohchi |first19=T. |last20=Yamamoto |first20=Y. |last21=Nagahama |first21=Y. |last22=Hagimoto |first22=Y. |last23=Wakabayashi |first23=H. |last24=Tagawa |first24=Y. |last25=Tsukamoto |first25=M. |last26=Iwamoto |first26=H. |last27=Saito |first27=M. |last28=Kadomura |first28=S. |last29=Nagashima |first29=N. |pages=1–4 |isbn=1-4244-0438-X }}</ref><ref>{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/4472451|title=2007 International Workshop on Physics of Semiconductor Devices|doi=10.1109/IWPSD.2007.4472451 |s2cid=25926459 |chapter=High-k/Metal Gates- from research to reality |date=2007 |last1=Narayanan |first1=V. |pages=42–45 |isbn=978-1-4244-1727-8 }}</ref><ref name="auto4"/><ref name="auto2">{{Cite web|url=https://spectrum.ieee.org/the-highk-solution|title=The High-k Solution - IEEE Spectrum|website=[[IEEE]]}}</ref><ref name="auto1">{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/4405765|title=2007 IEEE Custom Integrated Circuits Conference|doi=10.1109/CICC.2007.4405765 |s2cid=1589266 |chapter=High-K/Metal Gate Technology: A New Horizon |date=2007 |last1=Khare |first1=Mukesh |pages=417–420 |isbn=978-1-4244-0786-6 }}</ref> 

Since the 16nm/14nm node, Atomic layer etching (ALE) is increasingly used for etching as it offers higher precision than other etching methods. In production, plasma ALE is commonly used, which removes materials unidirectionally, creating structures with vertical walls. Thermal ALE can also be used to remove materials isotropically, in all directions at the same time but without the capability to create vertical walls. Plasma ALE was initially adopted for etching contacts in transistors, and since the 7nm node it is also used to create transistor structures by etching them.<ref name="auto8"/>

====Gate oxide and implants====
{{Main| self-aligned gate | doping (semiconductor) }}
Front-end surface engineering is followed by growth of the [[gate dielectric]] (traditionally [[silicon dioxide]]), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In [[dynamic random-access memory]] (DRAM) devices, storage [[capacitors]] are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer [[Qimonda]] implemented these capacitors with trenches etched deep into the silicon surface).

===Back-end-of-line (BEOL) processing===
{{Main|BEOL}}

====Metal layers====
Once the various semiconductor devices have been [[Integrated circuit#circuitLayers|created]], they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with ''back end'' of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO<sub>2</sub> or a [[silicate glass]], but recently new [[low-κ dielectric|low dielectric constant]] materials, also called low-κ dielectrics, are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO<sub>2</sub>), although materials with constants as low as 2.2 are being offered to chipmakers. 

BEoL has been used since 1995 at the 350nm and 250nm nodes (0.35 and 0.25 micron nodes), at the same time chemical mechanical polishing began to be employed. At the time, 2 metal layers for interconnect, also called metallization<ref>{{cite book | url=https://books.google.com/books?id=nC7wCAAAQBAJ&dq=integrated+circuit+metallization&pg=PA276 | title=Technology of Integrated Circuits | isbn=978-3-662-04160-4 | last1=Widmann | first1=D. | last2=Mader | first2=H. | last3=Friedrich | first3=H. | date=9 March 2013 | publisher=Springer }}</ref> was state-of-the-art.<ref>{{cite web | url=https://www.chiphistory.org/35-beol-origins-the-chip-history-center | title=BEOL Wiring Process for CMOS Logic }}</ref>

Since the 22nm node, some manufacturers have added a new process called middle-of-line (MOL) which connects the transistors to the rest of the interconnect made in the BEoL process. The MOL is often based on tungsten and has upper and lower layers: the lower layer connects the junctions of the transistors, and an upper layer which is a tungsten plug that connects the transistors to the interconnect. Intel at the 10nm node introduced contact-over-active-gate (COAG) which, instead of placing the contact for connecting the transistor close to the gate of the transistor, places it directly over the gate of the transistor to improve transistor density.<ref name="auto7">{{Cite web|url=https://semiengineering.com/racing-to-107nm/|title=The Race To 10/7nm|first=Mark|last=LaPedus|date=May 22, 2017|website=Semiconductor Engineering}}</ref>

====Interconnect====
{{Main| interconnect (integrated circuits) }}
[[Image:Siliconchip by shapeshifter.png|right|thumb|350px|Synthetic detail of a [[standard cell]] through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green)]]

Historically, the metal wires have been composed '''[[aluminum interconnects|of aluminum]]'''.  In this approach to wiring (often called ''subtractive aluminum''), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires.  Dielectric material is then deposited over the exposed wires.  The various metal layers are interconnected by etching holes (called "''vias")'' in the insulating material and then depositing [[tungsten]] in them with a [[chemical vapor deposition|CVD]] technique using [[tungsten hexafluoride]]; this approach can still be (and often is) used in the fabrication of many memory chips such as [[dynamic random-access memory]] (DRAM), because the number of interconnect levels can be small (no more than four). The aluminum was sometimes alloyed with copper for preventing recrystallization. Gold was also used in interconnects in early chips.<ref>{{cite book | url=https://books.google.com/books?id=jq3cdQd9XpwC&dq=aluminum+silicon+interconnect&pg=PA397 | isbn=978-3-540-43181-7 | title=Chemical-Mechanical Planarization of Semiconductor Materials | date=26 January 2004 | publisher=Springer }}</ref>

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern [[microprocessor]], the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to '''[[copper interconnect]]''' layer)<ref>{{cite book | url=https://books.google.com/books?id=UUFwuIYrSrQC&q=aluminum+replaced+by+copper+interconnect | isbn=978-1-4419-0076-0 | title=Copper Interconnect Technology | date=22 January 2010 | publisher=Springer }}</ref> alongside a change in dielectric material in the interconnect (from silicon dioxides to newer [[low-κ dielectric|low-κ]] insulators).<ref>{{Cite web|url=https://www.researchgate.net/publication/324645796|title=Introduction to Copper / Low-K Interconnects & Electromigration Fundamentals}}</ref><ref>{{Cite book|url=https://onlinelibrary.wiley.com/doi/10.1002/9781119963677.ch1|title=Low- k Materials: Recent Advances|first1=Geraud|last1=Dubois|first2=Willi|last2=Volksen|chapter=Low- ''k'' Materials: Recent Advances |editor-first1=Mikhail R.|editor-last1=Baklanov|editor-first2=Paul S.|editor-last2=Ho|editor-first3=Ehrenfried|editor-last3=Zschech|date=February 24, 2012|publisher=Wiley|pages=1–33|via=CrossRef|doi=10.1002/9781119963677.ch1|isbn=978-0-470-66254-0 }}</ref> This performance enhancement also comes at a reduced cost via [[Copper interconnect#Patterning|damascene]] processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP ([[chemical-mechanical planarization]]) is the primary processing method to achieve such planarization, although dry ''etch back'' is still sometimes employed when the number of interconnect levels is no more than three. Copper interconnects use an electrically conductive barrier layer to prevent the copper from diffusing into ("poisoning") its surroundings, often made of tantalum nitride.<ref>{{cite journal | pmc=7664900 | date=2020 | last1=Li | first1=Z. | last2=Tian | first2=Y. | last3=Teng | first3=C. | last4=Cao | first4=H. | title=Recent Advances in Barrier Layer of Cu Interconnects | journal=Materials | volume=13 | issue=21 | page=5049 | doi=10.3390/ma13215049 | pmid=33182434 | bibcode=2020Mate...13.5049L | doi-access=free }}</ref><ref name="auto7"/> In 1997, IBM was the first to adopt copper interconnects.<ref>{{cite web | url=https://www.chiphistory.org/ibm-s-development-of-copper-interconnect-for-ics | title=Ibm's Development of Copper Interconnect for Integrated Circuit }}</ref>

In 2014, Applied Materials proposed the use of cobalt in interconnects at the 22nm node, used for encapsulating copper interconnects in cobalt to prevent electromigration, replacing tantalum nitride since it needs to be thicker than cobalt in this application.<ref name="auto7"/><ref>{{cite web | url=https://www.eetimes.com/cobalt-encapsulation-extends-copper-to-10nm/ | title=Cobalt Encapsulation Extends Copper to 10nm | date=13 May 2014 }}</ref>