Editing SPARC (section)

====ALU operations====
Arithmetic and logical instructions also use a three-operand format, with the first two being the operands and the last being the location to store the result. The middle operand can be a register or a 13-bit signed integer constant; the other operands are registers. Any of the register operands may point to G0; pointing the result to G0 discards the results, which can be used for tests. Examples include:<ref name=ncsu/>

 add %L1,%L2,%L3   !add the values in %L1 and %L2 and put the result in %L3
 add %L1,1,%L1     !increment %L1
 add %G0,%G0,%L4   !clear any value in %L4

The list of mathematical instructions is {{code|ADD}}, {{code|SUB}}, {{code|AND}}, {{code|OR}}, {{code|XOR}}, and negated versions {{code|ANDN}}, {{code|ORN}}, and {{code|XNOR}}. One quirk of the SPARC design is that most arithmetic instructions come in pairs, with one version setting the NZVC condition code bits in the [[status register]], and the other not setting them, with the default being ''not'' to set the codes. This is so that the compiler has a way to move instructions around when trying to fill delay slots. If one wants the condition codes to be set, this is indicated by adding {{code|cc}} to the instruction:<ref name=ncsu/>

 subcc %L1,10,%G0  !compare %L1 to 10 and ignore the result, but set the flags

add and sub also have another modifier, X, which indicates whether the operation should set the carry bit:

 addx %L1,100,%L1  !add 100 to the value in %L1 and track carry

SPARC V7 does not have multiplication or division instructions, but it does have {{code|MULSCC}}, which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product. This was because {{code|MULSCC}} can complete over one clock cycle in keeping with the RISC philosophy.  SPARC V8 added {{code|UMUL}} (unsigned multiply), {{code|SMUL}} (signed multiply), {{code|UDIV}} (unsigned divide), and {{code|SDIV}} (signed divide) instructions, with both versions that do not update the condition codes and versions that do.  {{code|MULSCC}} and the multiply instructions use the Y register to hold the upper 32 bits of the product; the divide instructions use it to hold the upper 32 bits of the dividend.  The {{code|RDY}} instruction reads the value of the Y register into a general-purpose register; the {{code|WRY}} instruction writes the value of a general-purpose register to the Y register.<ref name="sparc-v8-whitepaper" />{{rp|page=32}}  SPARC V9 added {{code|MULX}}, which multiplies two 64-bit values and produces a 64-bit result, {{code|SDIVX}}, which divides a 64-bit signed dividend by a 64-bit signed divisor and produces a 64-bit signed quotient, and {{code|UDIVX}}, which divides a 64-bit unsigned dividend by a 64-bit unsigned divisor and produces a 64-bit signed quotient; none of those instructions use the Y register.<ref name="sparc-v9-whitepaper" />{{rp|page=199}}