Editing Motorola 88000 (section)

== Implementations ==
[[Image:Motorola MC88100RC20 CPU overhead view.jpg|thumb|right|Motorola 88100 RISC CPU]]
The first implementation of the 88000 ISA was the [[MC88100]] [[microprocessor]], which included an integrated [[floating point unit|FPU]]. Mated to this was the MC88200 [[Memory management unit|MMU]] and [[CPU cache|cache]] controller. The idea behind this splitting of duties was to allow [[multiprocessor]] systems to be built more easily; a single MC88200 could support up to four MC88100s. However, this also meant that building the most basic system, with a single processor, required both chips and considerable wiring between them, driving up costs. This was likely to be another major reason for the 88000's limited success.

The MC88100 implemented a 'Master/Checker' capability for fault tolerance employing two or more redundant MC88100s:
<blockquote>In this application, two processors are wired together. The master processor (PCE negated) operates normally. The checker processor (PCE asserted) places all of its outputs in the high impedance state except ERR; all outputs are monitored as inputs. The checker processor performs the same operations as the master processor and compares its internal results with the results read from the high-impedance pins. If a mismatch occurs between the master and checker, the checker asserts ERR. External logic must then determine the appropriate action for the system.<ref>{{Cite web |url=http://www.bitsavers.org/components/motorola/88000/MC88100_RISC_Microprocessor_Users_Manual_2ed_1990.pdf#page=165 |title=MC88100 RISC Microprocessor User's Manual |page=165(4.3.5) |accessdate=2025-01-15}}</ref></blockquote>

[[Image:Motorola XC88110RS50G CPU overhead view.jpg|thumb|right|130px|Motorola 88110 RISC CPU]]
The packaging & cost issue was later addressed by the [[superscalar]] [[MC88110]], which combined the CPU, FPU, MMU, and [[L1 cache]] into a single package. An additional modification, made at the behest of [[Massachusetts Institute of Technology|MIT]]'s *T project, resulted in the MC88110MP, including on-chip communications for use in multi-processor systems.<ref name="*T:">{{cite web |title=*T: Integrated Building Blocks for Parallel Computing |url=http://csg.csail.mit.edu/pubs/memos/Memo-351/Memo-351.pdf |date=July 28, 1993 |publisher=Massachusetts Institute of Technology |author=Papadopoulos|access-date=2009-06-16|display-authors=etal}}</ref> A version capable of speeds up to 100&nbsp;MHz was planned as the MC88120, but was never built.

An implementation for embedded applications, the MC88300, was under development during the early 1990s, but was eventually canceled. [[Ford Motor Company]] had planned to use the chips, which alongside adoption by telecommunications vendors had been viewed as guaranteeing the viability of the architecture indefinitely.<ref name="unigramx19910617_ford">{{ cite news | url=https://archive.org/details/UnigramX1991314-365/page/n150/mode/1up | title=Ford Secures 88000 RISC Future | work=Unigram/X | date=17 June 1991 | access-date=25 July 2024 | pages=1 }}</ref> Motorola offered a PowerPC design as a replacement, which Ford accepted.<ref>{{cite magazine |url=http://www.nextcomputers.org/NeXTfiles/Articles/NeXTWORLD/NeXTWORLD_Extra/92.06.June.NWE/92.06.June.NWExtra05.html |title= Motorola looks to 68060 chip |first=Simson |last=Garfinkel |magazine= NeXTWORLD |date=June 1992}}</ref>