Editing MIPS architecture (section)

=== MIPS II ===

MIPS II removed the load delay slot<ref name=Sweetman1999/>{{rp|41}} and added several sets of instructions. For shared-memory multiprocessing, the ''Synchronize Shared Memory'', ''Load Linked Word'', and ''Store Conditional Word'' instructions were added.<ref name="mips-ll-sc">{{Cite web |url=https://www.cs.auckland.ac.nz/compsci313s2c/resources/MIPSLLSC.pdf#page=9 |title=APPLICATION NOTE MIPS R4000 Synchronization Primitives |page=5 |accessdate=2023-12-27 |archive-date=December 27, 2023 |archive-url=https://web.archive.org/web/20231227143936/https://www.cs.auckland.ac.nz/compsci313s2c/resources/MIPSLLSC.pdf#page=9 |url-status=live }}</ref> A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given ''branch-likely'' versions that executed the instruction in the branch delay slot only if the branch is taken.<ref name=Sweetman1999/>{{rp|40}} These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot.<ref name=Sweetman1999/>{{rp|212}} Doubleword load and store instructions for COP1–3 were added. Consistent with other memory access instructions, these loads and stores required the doubleword to be naturally aligned.

The instruction set for the floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands. A set of instructions that converted single- and double-precision floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by the instruction instead of the Floating Point Control and Status Register.