Editing JFET (section)

=== Constant-current region ===
The drain current in the ''saturation'' or ''active''<ref>{{cite web |title=Junction Field Effect Transistor |url=https://www.electronics-tutorials.ws/transistor/tran_5.html |website=Electronics Tutorials |quote=Saturation or Active Region}}</ref><ref name=":2" /> or ''pinch-off region''<ref>{{cite web |last=Scholberg |first=Kate |date=2017-03-23 |title=What is the meaning of "pinch-off region"? |url=https://webhome.phy.duke.edu/~schol/phy271/faqs/faq17/node7.html |quote=The "pinch-off region" (or "saturation region") refers to operation of a FET with <math>V_{ds}</math> more than a few volts.}}</ref> is often approximated in terms of gate bias as<ref name=kumar/>

: <math>I_\text{DS} = I_\text{DSS} \left(1 - \frac{V_\text{GS}}{V_\text{P}}\right)^2,</math>

where ''I''<sub>DSS</sub> is the saturation current at zero gate–source voltage, i.e. the maximum current that can flow through the FET from drain to source at any (permissible) drain-to-source voltage (see, e. g., the ''I''–''V'' characteristics diagram above).

In the ''saturation region'', the JFET drain current is most significantly affected by the gate–source voltage and barely affected by the drain–source voltage.

If the channel doping is uniform, such that the depletion region thickness will grow in proportion to the square root of the absolute value of the gate–source voltage, then the channel thickness ''b'' can be expressed in terms of the zero-bias channel thickness ''a'' as<ref>{{Cite web |last=Storr |first=Wayne |date=2013-09-03 |title=Junction Field Effect Transistor or JFET Tutorial |url=https://www.electronics-tutorials.ws/transistor/tran_5.html |access-date=2022-10-07 |website=Basic Electronics Tutorials |language=en}}</ref>{{Failed verification|date=October 2022}}

: <math>b = a \left(1 - \sqrt{\frac{V_\text{GS}}{V_\text{P}}}\right),</math>

where 
: ''V''<sub>P</sub> is the pinch-off voltage{{snd}} the gate–source voltage at which the channel thickness goes to zero,
: ''a'' is the channel thickness at zero gate–source voltage.