Editing Intel 8008 (section)

==Interrupts==
[[File:JB.SIM8-01.jpg|thumb|Intel SIM8-01 CPU board, possibly the first use of the 8008. Contains 1K bytes of RAM in 32 chips and 2K byte of EPROM in eight chips. No provision for interrupts.]]
[[Interrupt|Interrupts]] on the 8008 are only partially implemented. After the INT line is asserted, the 8008 acknowledges the interrupt by outputting a state code of S0,S1,S2 = 011 at T1I time. At the subsequent instruction fetch cycle, an instruction is "jammed" (Intel's word) by external hardware on the bus. Typically this is a one-byte RST instruction.

At this point, there is a problem. The 8008 has no provision to save its [[architectural state]]. The 8008 can only write to memory via an address in the HL register pair. When interrupted, there is no mechanism to save HL so there is no way to save the other registers and flags via HL. Because of this, some sort of external memory device such as a hardware [[Stack (abstract data type)|stack]] or a pair of read/write [[Hardware register|registers]] must be attached to the 8008 via the I/O ports to help save the state of the 8008.<ref>{{cite journal |last1=Chamberklin |first1=Hal |title="Add a Stack to your 8008 |journal=Byte |date=October 1975 |volume=0 |issue=2 |pages=52–56 |url=https://archive.org/details/byte-magazine-1975-10/page/n53/mode/2up |access-date=5 October 2024}}</ref>