Editing GE 645 (section)

=== Functional Units ===
[[File:Ge645-processor.png|thumb|330x330px|GE 645 processor Functional Units]]The 645 processor was divided into four major functional units these were:<ref name="AH82-00" />

* '''Appending Unit:''' 
** Controls data I/O from memory
** Controls memory selection and interleave
** Carries out Memory appending
** Control fault recognition
** Does power on/off sequencing
* '''Associative Memory Unit:'''
** Consists of Associative Memory made up of 16 x 60-bit Registers<ref name="Schroeder">{{cite conference |last1=Schroeder |first1=Michael D. |book-title=Proceedings of the SIGOPS workshop on System performance evaluation|title=Performance of the GE-645 Associative Memory While Multics is in Operation |date=1971 |pages=227–245 |doi=10.1145/800024.808361 |url=https://dl.acm.org/doi/abs/10.1145/800024.808361 |publisher=Association for Computing Machinery|isbn=9781450373821 |s2cid=44850627 }}</ref>
** Registers point to most recently used segment (Segment Descriptor Word) or most recently used Page (Page Table)
** Performs the function of what would now be classed as a TLB.
* '''Control Unit:'''
** Performs all control functions
** Performs Address modification
** Controls the [[CPU modes|processor mode]] (master, slave, absolute)
** Interrupt recognition/handling
** Opcode decoding
* '''Operations Unit:'''
** Performs fractional and integer divisions and multiplications.
** Performs automatic alignment of floating-point numbers for addition and subtraction.
** Performs inverted divisions on floating-point numbers.
** Performs automatic normalization of floating-point resultants.
** Performs shifts.
** Performs indicator register loading and storing.
** Performs timer register loading and decrementing.

One of the key differences from the GE 635 was the addition of "appending unit" (APU) which was used to implement a hybrid "Paged Segmentation" model of [[virtual memory]]. The APU was also used to implement a [[single-level store]] which is one of the fundamental abstraction that Multics is built around. The instruction format was also extended with the previously unused bit 29 controlling whether the operand address of an instruction used an 18-bit format (bit 29 = 0) or one that was made up of a 3-bit Base Register address with a 15-bit offset (bit 29 = 1).<ref name="LSB0468">{{cite web |title=GE-645 System Manual |url=http://bitsavers.org/pdf/ge/GE-645/LSB0468_GE-645_System_Manual_Jan1968.pdf |publisher=General Electric |access-date=26 September 2023 |ref=LSB0468 |date=January 1968}}</ref>{{rp|pages=18,22}}<ref name="AH82-00">{{cite web |date=May 1972 |title=MODEL 645 PROCESSOR REFERENCE MANUAL |url=http://people.csail.mit.edu/saltzer/Multics/MHP-Saltzer-060508/bookcases/Manuals/AH82-00.ocr.pdf |access-date=26 September 2023 |publisher=Honeywell Information Systems Inc. |ref=AH82-00}}</ref>

The instruction format with bit 29 set to 1 is:
<pre>
                          1 1       2 2 2 2 3    3
        0 2 3             7 8       6 7 8 9 0    5
       +---+---------------+---------+-+-+-+------+
       |BR |       Y       |  OP     |0|I|1| Tag  |
       +---+---------------+---------+-+-+-+------+
</pre>
* '''B''' is the base register field
* '''Y''' is the address field (15 bits), addressing 32KW
* '''OP''' is the opcode (9 bits), the additional bit 27 is the ''opcode extension bit''.
* '''I''' is the interrupt inhibit bit.
* '''Tag''' indicates the type of address modification to be performed; some additional tags are supported by the GE 645.<ref name="LSB0468" />{{rp|pages=19-20}}