Jump to content
Main menu
Main menu
move to sidebar
hide
Navigation
Main page
Recent changes
Random page
Help about MediaWiki
Special pages
Niidae Wiki
Search
Search
Appearance
Create account
Log in
Personal tools
Create account
Log in
Pages for logged out editors
learn more
Contributions
Talk
Editing
Field-programmable gate array
(section)
Page
Discussion
English
Read
Edit
View history
Tools
Tools
move to sidebar
hide
Actions
Read
Edit
View history
General
What links here
Related changes
Page information
Appearance
move to sidebar
hide
Warning:
You are not logged in. Your IP address will be publicly visible if you make any edits. If you
log in
or
create an account
, your edits will be attributed to your username, along with other benefits.
Anti-spam check. Do
not
fill this in!
=== Hard blocks === Modern FPGA families expand upon the above capabilities to include higher-level functionality fixed in silicon. Having these common functions embedded in the circuit reduces the area required and gives those functions increased performance compared to building them from logical primitives. Examples of these include [[Binary multiplier|multipliers]], generic [[Digital signal processor|DSP blocks]], [[Microprocessor|embedded processors]], high-speed I/O logic and embedded [[Computer memory|memories]]. Higher-end FPGAs can contain high-speed [[multi-gigabit transceiver]]s and ''hard IP cores'' such as [[processor core]]s, [[Ethernet]] [[Medium access control|medium access control units]], [[Conventional PCI|PCI]] or [[PCI Express]] controllers, and external [[memory controller]]s. These cores exist alongside the programmable fabric, but they are built out of [[transistor]]s instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. The multi-gigabit transceivers also contain high-performance [[signal conditioning]] circuitry along with high-speed serializers and deserializers, components that cannot be built out of LUTs. Higher-level physical layer (PHY) functionality such as [[line coding]] may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.
Summary:
Please note that all contributions to Niidae Wiki may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see
Encyclopedia:Copyrights
for details).
Do not submit copyrighted work without permission!
Cancel
Editing help
(opens in new window)
Search
Search
Editing
Field-programmable gate array
(section)
Add topic