Editing Dynamic random-access memory (section)

===Memory timing===
{{Main|Memory timings}}
Many parameters are required to fully describe the timing of DRAM operation. Here are some examples for two timing grades of asynchronous DRAM, from a data sheet published in 1998:<ref name="Micron1">{{cite web|url=http://download.micron.com/pdf/datasheets/dram/d47b.pdf|title=Micron 4 Meg x 4 EDO DRAM data sheet|website=micron.com|access-date=8 May 2018|url-status=dead|archive-url=https://web.archive.org/web/20070927174618/http://download.micron.com/pdf/datasheets/dram/d47b.pdf|archive-date=27 September 2007}}</ref>

{|class="wikitable" style="text-align:center;"
|+ Asynchronous DRAM typical timing
|-
!||"50&nbsp;ns"||"60&nbsp;ns"||Description
|-
|''t''<sub>RC</sub>||84&nbsp;ns||104&nbsp;ns||align=left|Random read or write cycle time (from one full /RAS cycle to another)
|-
|''t''<sub>RAC</sub>||50&nbsp;ns||60&nbsp;ns||align=left|Access time: /RAS low to valid data out
|-
|''t''<sub>RCD</sub>||11&nbsp;ns||14&nbsp;ns||align=left|/RAS low to /CAS low time
|-
|''t''<sub>RAS</sub>||50&nbsp;ns||60&nbsp;ns||align=left|/RAS pulse width (minimum /RAS low time)
|-
|''t''<sub>RP</sub>||30&nbsp;ns||40&nbsp;ns||align=left|/RAS precharge time (minimum /RAS high time)
|-
|''t''<sub>PC</sub>||20&nbsp;ns||25&nbsp;ns||align=left|Page-mode read or write cycle time (/CAS to /CAS)
|-
|''t''<sub>AA</sub>||25&nbsp;ns||30&nbsp;ns||align=left|Access time: Column address valid to valid data out (includes address [[setup time]] before /CAS low)
|-
|''t''<sub>CAC</sub>||13&nbsp;ns||15&nbsp;ns||align=left|Access time: /CAS low to valid data out
|-
|''t''<sub>CAS</sub>||8&nbsp;ns||10&nbsp;ns||align=left|/CAS low pulse width minimum
|}
Thus, the generally quoted number is the /RAS low to valid data out time. This is the time to open a row, settle the sense amplifiers, and deliver the selected column data to the output.  This is also the minimum /RAS low time, which includes the time for the amplified data to be delivered back to recharge the cells. The time to read additional bits from an open page is much less, defined by the /CAS to /CAS cycle time. The quoted number is the clearest way to compare between the performance of different DRAM memories, as it sets the slower limit regardless of the row length or page size. Bigger arrays forcibly result in larger bit line capacitance and longer propagation delays, which cause this time to increase as the sense amplifier settling time is dependent on both the capacitance as well as the propagation latency. This is countered in modern DRAM chips by instead integrating many more complete DRAM arrays within a single chip, to accommodate more capacity without becoming too slow.

When such a RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle. For example, when accessed by a 100&nbsp;MHz state machine (i.e. a 10&nbsp;ns clock), the 50&nbsp;ns DRAM can perform the first read in five clock cycles, and additional reads within the same page every two clock cycles. This was generally described as {{nowrap|"5-2-2-2"}} timing, as bursts of four reads within a page were common.

When describing synchronous memory, timing is described by clock cycle counts separated by hyphens. These numbers represent {{nowrap|''t''<sub>CL</sub>-''t''<sub>RCD</sub>-''t''<sub>RP</sub>-''t''<sub>RAS</sub>}} in multiples of the DRAM clock cycle time. Note that this is half of the data transfer rate when [[double data rate]] signaling is used. JEDEC standard PC3200 timing is {{nowrap|3-4-4-8}}<ref>{{cite web|title=Corsair CMX1024-3200 (1&nbsp;GByte, two bank unbuffered DDR SDRAM DIMM)|url=http://www.corsairmemory.com/corsair/products/specs/cmx1024-3200.pdf|archive-url=https://web.archive.org/web/20080911032322/http://www.corsairmemory.com/_datasheets/cmx1024-3200.pdf|archive-date=11 September 2008|date=December 2003}}</ref> with a 200&nbsp;MHz clock, while premium-priced high performance PC3200 DDR DRAM DIMM might be operated at {{nowrap|2-2-2-5}} timing.<ref>{{cite web|title=Corsair TWINX1024-3200XL dual-channel memory kit|url=http://www.corsairmemory.com/corsair/products/specs/twinx1024-3200xl.pdf|archive-url=https://web.archive.org/web/20061207112238/http://www.corsairmemory.com/corsair/products/specs/twinx1024-3200xl.pdf|archive-date=7 December 2006|date=May 2004}}</ref>
{|class="wikitable" style="text-align:center;"
|+ Synchronous DRAM typical timing
!rowspan=2 colspan=2| ||colspan=2|PC-3200 (DDR-400)||colspan=2|PC2-6400 (DDR2-800)||colspan=2|PC3-12800 (DDR3-1600)||rowspan=2|Description
|-
!cycles||time||cycles||time||cycles||time
|-
!rowspan=2|''t''<sub>CL</sub>||Typical
|3||15&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns
|rowspan=2 align=left|/CAS low to valid data out (equivalent to ''t''<sub>CAC</sub>)
|-
!Fast
|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns
|-
!rowspan=2|''t''<sub>RCD</sub>||Typical
|4||20&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns
|rowspan=2 align=left|/RAS low to /CAS low time
|-
!Fast
|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns
|-
!rowspan=2|''t''<sub>RP</sub>||Typical
|4||20&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns
|rowspan=2 align=left|/RAS precharge time (minimum precharge to active time)
|-
!Fast
|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns
|-
!rowspan=2|''t''<sub>RAS</sub>||Typical
|8||40&nbsp;ns||16||40&nbsp;ns||27||33.75&nbsp;ns
|rowspan=2 align=left|Row active time (minimum active to precharge time)
|-
!Fast
|5||25&nbsp;ns||12||30&nbsp;ns||24||30&nbsp;ns
|}
Minimum random access time has improved from ''t''<sub>RAC</sub>&nbsp;=&nbsp;50&nbsp;ns to {{nowrap|1=''t''<sub>RCD</sub> + ''t''<sub>CL</sub> = 22.5&nbsp;ns}}, and even the premium 20&nbsp;ns variety is only 2.5 times faster than the asynchronous DRAM. [[CAS latency]] has improved even less, from {{nowrap|1=''t''<sub>CAC</sub> = 13&nbsp;ns}} to 10&nbsp;ns. However, the DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output two words every 1.25&nbsp;ns {{gaps|(1|600|u=Mword/s)}}, while the EDO DRAM can output one word per ''t''<sub>PC</sub>&nbsp;=&nbsp;20&nbsp;ns (50&nbsp;Mword/s).

====Timing abbreviations====
{|
|
*''t''<sub>CL</sub> – CAS latency
*''t''<sub>CR</sub> – Command rate
*''t''<sub>PTP</sub> – precharge to precharge delay
*''t''<sub>RAS</sub> – RAS active time
*''t''<sub>RCD</sub> – RAS to CAS delay
*''t''<sub>REF</sub> – Refresh period
*''t''<sub>RFC</sub> – Row refresh cycle time
*''t''<sub>RP</sub> – RAS precharge
|
*''t''<sub>RRD</sub> – RAS to RAS delay
*''t''<sub>RTP</sub> – Read to precharge delay
*''t''<sub>RTR</sub> – Read to read delay
*''t''<sub>RTW</sub> – Read to write delay
*''t''<sub>WR</sub> – Write recovery time
*''t''<sub>WTP</sub> – Write to precharge delay
*''t''<sub>WTR</sub> – Write to read delay
*''t''<sub>WTW</sub> – Write to write delay
|}