Editing DIMM (section)

== Ranking ==
{{main|Memory rank}}
Sometimes memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a '''rank'''. Ranks that share the same slot, only one rank may be accessed at any given time; it is specified by activating the corresponding rank's chip select (CS) signal. The other ranks on the module are deactivated for the duration of the operation by having their corresponding CS signals deactivated. DIMMs are currently being commonly manufactured with up to four ranks per module. Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs.

After a memory word is fetched, the memory is typically inaccessible for an extended period of time while the sense amplifiers are charged for access of the next cell. By interleaving the memory (e.g. cells 0, 4, 8, etc. are stored together in one rank), sequential memory accesses can be performed more rapidly because sense amplifiers have 3 cycles of idle time for recharging, between accesses.

DIMMs are often referred to as "single-sided" or "[[Double-sided RAM|double-sided]]" to describe whether the DRAM chips are located on one or both sides of the module's [[printed circuit board]] (PCB). However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed.

[[JEDEC]] decided that the terms "dual-sided", "double-sided", or "dual-banked" were not correct when applied to [[registered DIMM]]s (RDIMMs).