Editing DEC Alpha (section)

==Registers==
{| class="infobox" style="font-size:88%;width:34em;"
|-
|+ DEC Alpha registers
|-
|
{| style="font-size:88%;"
|- 
| style="width:10px; text-align:left;"  | <sup>6</sup><sub>3</sub>
| style="width:50px; text-align:center;"| . . .
| style="width:10px; text-align:right;" | <sup>4</sup><sub>7</sub>
| style="width:50px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>3</sup><sub>1</sub>
| style="width:50px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:50px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- 
|colspan="11" | '''General-purpose registers'''<br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| R0
| style="background:white; color:black;"| R0
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| R1
| style="background:white; color:black;"| R1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| R2
| style="background:white; color:black;"| R2
|-
| style="text-align:center;" colspan="10"| •
| style="background:white; color:black;"| &nbsp;
|-
| style="text-align:center;" colspan="10"| •
| style="background:white; color:black;"| &nbsp;
|-
| style="text-align:center;" colspan="10"| •
| style="background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| R29
| style="background:white; color:black;"| R29
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| R30
| style="background:white; color:black;"| R30
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| {{0|''(zero)''}}R31 ''(zero)''
| style="background:white; color:black; white-space: nowrap"| R31, always zero
|- 
|colspan="11" | '''Floating-point registers'''<br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| F0
| style="background:white; color:black;"| F0
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| F1
| style="background:white; color:black;"| F1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| F2
| style="background:white; color:black;"| F2
|-
| style="text-align:center;" colspan="10"| •
| style="background:white; color:black;"| &nbsp;
|-
| style="text-align:center;" colspan="10"| •
| style="background:white; color:black;"| &nbsp;
|-
| style="text-align:center;" colspan="10"| •
| style="background:white; color:black;"| &nbsp;
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| F29
| style="background:white; color:black;"| F29
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| F30
| style="background:white; color:black;"| F30
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| {{0|''(zero)''}}F31 ''(zero)''
| style="background:white; color:black"| F31, always zero
|-
|colspan="11" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center;padding-left:2.5em" colspan="8"| PC
| style="text-align:center;" colspan="1"| 0
| style="text-align:center;" colspan="1"| 0
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|-
|colspan="11" | '''Control registers'''<br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| LR0
| style="background:white; color:black;"| '''L'''ock '''R'''egister 0 <!--How many bits wide are these registers?-->
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| LR1
| style="background:white; color:black;"| '''L'''ock '''R'''egister 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="10"| FPCR
| style="background:white; color:black;"| '''FP''' '''C'''ontrol '''R'''egister <!--How many bits wide is this register?-->
|}
|}

The architecture defines a set of 32 integer [[Processor register|register]]s and a set of 32 floating-point registers in addition to a [[program counter]], two lock registers and a floating-point control register (FPCR). It also defines registers that were optional, implemented only if the implementation required them. Lastly, registers for [[PALcode]] are defined.

The integer registers are denoted by R0 to R31 and floating-point registers are denoted by F0 to F31. The R31 and F31 registers are hardwired to zero and writes to those registers by instructions are ignored. Digital considered using a combined register file, but a split register file was determined to be better, as it enables two-chip implementations to have a register file located on each chip and integer-only implementations to omit the floating-point register file containing the floating-point registers. A split register file was also determined to be more suitable for multiple instruction issue due to the reduced number of read and write ports. The number of registers per register file was also considered, with 32 and 64 being contenders. Digital concluded that 32 registers was more suitable as it required less [[Die (integrated circuit)|die]] space, which improves clock frequencies. This number of registers was deemed not to be a major issue in respect to performance and future growth, as thirty-two registers could support at least eight-way instruction issue.

The [[program counter]] is a 64-bit register which contains a longword-aligned virtual byte address, that is, the low two bits of the program counter are always zero. The PC is incremented by four to the address of the next instruction when an instruction is decoded. A lock flag and locked physical address register are used by the load-locked and store-conditional instructions for multiprocessor support. The floating-point control register (FPCR) is a 64-bit register defined by the architecture intended for use by Alpha implementations with [[IEEE 754]]-compliant floating-point hardware.