Editing Counter (digital) (section)

===Binary counter <span class="anchor" id="Binary counter"></span>===

A '''binary counter''' is a digital counter that directly represents the count as a binary number. A binary counter is a MOD-{{math|2<sup>''n''</sup>}} counter, where ''n'' is the number of flip-flops used to store the count. For example, the illustrations below show the behavior of a 5-bit binary counter, which has 32 ({{math|2<sup>5</sup>}}) states and is therefore a MOD-32 counter:

<gallery widths="350px">
File:Binary counter.gif|Count sequence of a 5-bit binary up-counter
File:Bin counter timing d.jpg|Voltage changes on the outputs of a 5-bit binary counter as it counts up from 0 to 31 (left to right), with most-significant bit on top row and successively less-significant bits in the rows below
</gallery>

====Asynchronous binary counter====

An asynchronous binary counter, or binary ripple counter, is a "chain" of toggle (T) flip-flops in which the least-significant flip-flop (bit 0) is clocked by an external signal (the counter input clock), and all other flip-flops are clocked by the output of the nearest, less significant flip-flop (e.g., bit 0 clocks the bit 1 flip-flop, bit 1 clocks bit 2, etc.). When implemented with discrete flip-flops, ripple counters are commonly implemented with [[Flip-flop (electronics)#JK flip-flop|JK flip-flops]], with each flip-flop configured to toggle when clocked (i.e., J and K are both connected to logic high).

[[File:Async counter JK nbit.svg|400px|border|Schematic diagram of an n-bit ripple counter constructed from [[JK flip flop]]s. In this counter, the first flip-flop is clocked by rising edges; all other flip-flops in the chain are clocked by falling clock edges.]]

Each flip-flop is effectively a one-bit counter which increments its count (by toggling its output) once per clock cycle. It counts from zero to one and then, when the next clock arrives, it will overflow and start its count sequence over again at zero. Each output state persists for a full input clock cycle, and consequently the frequency of each flip-flop's output signal is exactly half that of its input clock. Additional flip-flops may be added to the chain to form a counter of any arbitrary word size (number of bits), with the output frequency of each bit equal to exactly half the frequency of its nearest, less significant bit.

<gallery heights="160px" widths="350px">
File:4020 Functional Diagram.svg|Functional diagram of a CMOS 4020, 14-bit ripple counter IC
File:RCA CD74HC4020E.jpg|Photograph of a CMOS 4020, 14-bit ripple counter IC ([[RCA]] CD74HC4020E)
</gallery>

====Synchronous binary counter====

The circuit shown below is a synchronous, up-counting four-bit binary counter implemented with JK flip-flops. Upon clock rising edge, bit 0 will always toggle, whereas other bits will toggle only when all less-significant bits are at a logic high state (i.e., Q1 toggles if Q0 is logic high; Q2 toggles if Q0 and Q1 are both high; and Q3 toggles if Q0, Q1, and Q2 are all high).

[[File:4 bit binary synchronous counter.svg|400px|border|Synchronous 4-bit binary counter using JK flip-flops]]

As in asynchronous counters, each flip-flop introduces a delay from input clock edge to output toggle, but in this case all flip-flops change state concurrently, and consequently the counter output will settle after only one flip-flop delay regardless of the number of bits.