Editing Central processing unit (section)

===Decode===
{{Further|Instruction set architecture#Instruction encoding}}

The instruction that the CPU fetches from memory determines what the CPU will do. In the decode step, performed by [[binary decoder]] circuitry known as the ''instruction decoder'', the instruction is converted into signals that control other parts of the CPU.

The way in which the instruction is interpreted is defined by the CPU's instruction set architecture (ISA).{{Efn|Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "PowerPC CPU" uses some variant of the PowerPC ISA. A CPU of a certain ISA can execute a different ISA by running an emulator.}} Often, one group of bits (that is, a "field") within the instruction, called the [[opcode]], indicates which operation is to be performed, while the remaining fields usually provide supplemental information required for the operation, such as the operands. Those operands may be specified as a constant value (called an immediate value), or as the location of a value that may be a [[processor register]] or a memory address, as determined by some [[addressing mode]].

In some CPU designs, the instruction decoder is implemented as a hardwired, unchangeable binary decoder circuit. In others, a [[microprogram]] is used to translate instructions into sets of CPU configuration signals that are applied sequentially over multiple clock pulses. In some cases the memory that stores the microprogram is rewritable, making it possible to change the way in which the CPU decodes instructions.