Editing CMOS (section)

== Power: switching and leakage ==
CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical [[application-specific integrated circuit|ASIC]] in a modern [[90 nanometer]] process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from V<sub>dd</sub> to V<sub>ss</sub> through the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:

=== Static dissipation ===

Both NMOS and PMOS transistors have a gate–source [[threshold voltage]] (V<sub>th</sub>), below which the current (called ''sub threshold'' current) through the device will drop exponentially. Historically, CMOS circuits operated at supply voltages much larger than their threshold voltages (V<sub>dd</sub> might have been 5&nbsp;V, and V<sub>th</sub> for both NMOS and PMOS might have been 700&nbsp;mV). A special type of the transistor used in some CMOS circuits is the [[native transistor]], with near zero [[threshold voltage]].

SiO<sub>2</sub> is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130&nbsp;nm technology with gate oxides of 20&nbsp;Å or thinner.

Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily. Furthermore, recent studies have shown that leakage power reduces due to aging effects as a trade-off for devices to become slower.<ref>{{cite book |first1=A.L.H. |last1=Martínez |first2=S. |last2=Khursheed |first3=D. |last3=Rossi |chapter=Leveraging CMOS Aging for Efficient Microelectronics Design |title=2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS) |publisher= |year=2020 |isbn= 978-1-7281-8187-5|pages=1–4 |doi=10.1109/IOLTS50870.2020.9159742|s2cid=225582202 }}</ref>

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a V<sub>th</sub> of 200&nbsp;mV has a significant [[subthreshold leakage]] current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. [[Multi-threshold CMOS]] (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high V<sub>th</sub> transistors are used when switching speed is not critical, while low V<sub>th</sub> transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional [[Leakage (electronics)|leakage]] component because of current [[Quantum tunnelling|tunnelling]] through the extremely thin gate dielectric. Using [[high-κ dielectric]]s instead of [[silicon dioxide]] that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.<ref>A good overview of leakage and reduction methods are explained in the book [https://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-25737-2 Leakage in Nanometer CMOS Technologies] {{webarchive|url=https://web.archive.org/web/20111202012235/http://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-25737-2 |date=2011-12-02 }} {{ISBN|0-387-25737-3}}.</ref>

=== Dynamic dissipation ===

==== Charging and discharging of load capacitances ====
CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from V<sub>DD</sub> to the load capacitance to charge it and then flows from the charged load capacitance (C<sub>L</sub>) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=C<sub>L</sub>V<sub>DD</sub> is thus transferred from V<sub>DD</sub> to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device: <math> P = 0.5 C V^2 f </math>.

Since most gates do not operate/switch at every [[Clock signal|clock cycle]], they are often accompanied by a factor <math>\alpha</math>, called the activity factor. Now, the dynamic power dissipation may be re-written as <math> P = \alpha C V^2 f </math>.

A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1.<ref>{{cite journal |first1=Konstantin |last1=Moiseev |first2=Avinoam |last2=Kolodny |first3=Shmuel |last3=Wimer |title=Timing-aware power-optimal ordering of signals |journal=ACM Trans. Des. Autom. Electron. Syst. |volume=13 |issue=4 |at=Article 65 |date=September 2008 |doi=10.1145/1391962.1391973 |citeseerx=10.1.1.222.9211|s2cid=18895687 }}</ref> If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

==== Short-circuit power ====
Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from V<sub>DD</sub> to ground, hence creating a [[short-circuit current]], sometimes called a ''crowbar'' current. Short-circuit power dissipation increases with the rise and fall time of the transistors.

This form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. Careful design which avoids weakly driven long skinny wires reduces this effect, but crowbar power can be a substantial part of dynamic CMOS power.