Editing Bus (computing) (section)

===First generation===
Early [[computer]] buses were bundles of wire that attached [[computer memory]] and peripherals. Anecdotally termed the ''digit trunk'' in the early Australian [[CSIRAC]] computer,<ref>{{cite book|last1=McCann|first1=Doug|last2=Thorne|first2=Peter|title=The Last of The First, CSIRAC: Australias First Computer|pages=8–11, 13, 91|publisher=University of Melbourne Computing Science|year=2000|url=https://cis.unimelb.edu.au/about/csirac/last-of-the-first|isbn=0-7340-2024-4}}</ref> they were named after electrical power buses, or [[busbar]]s. Almost always, there was one bus for memory, and one or more separate buses for peripherals. These were accessed by separate instructions, with completely different timings and protocols.

One of the first complications was the use of [[interrupt]]s. Early computer programs performed [[I/O]] by [[Busy waiting|waiting in a loop]] for the peripheral to become ready. This was a waste of time for programs that had other tasks to do. Also, if the program attempted to perform those other tasks, it might take too long for the program to check again, resulting in loss of data. Engineers thus arranged for the peripherals to interrupt the CPU. The interrupts had to be prioritized, because the CPU can only execute code for one peripheral at a time, and some devices are more time-critical than others.

High-end systems introduced the idea of [[channel controller]]s, which were essentially small computers dedicated to handling the input and output of a given bus. [[IBM]] introduced these on the [[IBM 709]] in 1958, and they became a common feature of their platforms. Other high-performance vendors like [[Control Data Corporation]] implemented similar designs. Generally, the channel controllers would do their best to run all of the bus operations internally, moving data when the CPU was known to be busy elsewhere if possible, and only using interrupts when necessary. This greatly reduced CPU load, and provided better overall system performance.

[[Image:Computer system bus.svg|thumb|right|400px |Single [[system bus]] ]]
To provide modularity, memory and I/O buses can be combined into a unified [[system bus]].<ref>{{cite book |title=The essentials of computer organization and architecture |author1=Linda Null |author2=Julia Lobur |publisher=Jones & Bartlett Learning |year=2006 |isbn=978-0-7637-3769-6 |edition=2nd |pages=33,179–181 |url=https://books.google.com/books?id=QGPHAl9GE-IC&pg=PA33 |url-status=live |archive-url=https://web.archive.org/web/20180117151308/https://books.google.com/books?id=QGPHAl9GE-IC&pg=PA33 |archive-date=2018-01-17 }}</ref> In this case, a single mechanical and electrical system can be used to connect together many of the system components, or in some cases, all of them.

Later computer programs began to share memory common to several CPUs. Access to this memory bus had to be prioritized, as well. The simple way to prioritize interrupts or bus access was with a [[Daisy chain (electrical engineering)|daisy chain]]. In this case signals will naturally flow through the bus in physical or logical order, eliminating the need for complex scheduling.