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====[[Pentium III]]==== * '''Katmai''' – [[250 nanometer|0.25 μm process technology]] ** Introduced February 26, 1999 ** Improved PII (i.e. P6-based core) now including [[Streaming SIMD Extensions]] (SSE) ** 9.5 million transistors ** 512 KB (512 × 1024 B) {{frac|1|2}} bandwidth L2 External cache ** 242-pin [[Slot 1]] SECC2 (Single Edge Contact cartridge 2) processor package ** System bus clock rate 100 MHz, 133 MHz (B-models) ** Slot 1 ** Family 6 model 7 ** Variants *** 450, 500 MHz introduced February 26, 1999 *** 550 MHz introduced May 17, 1999 *** 600 MHz introduced August 2, 1999 *** 533, 600 MHz introduced (133 MHz bus clock rate) September 27, 1999 * '''Coppermine''' – [[180 nanometer|0.18 μm process technology]] ** Introduced October 25, 1999 ** 28.1 million transistors ** 256 KB (512 × 1024 B) Advanced Transfer L2 cache (integrated) ** 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin [[FC-PGA]] (flip-chip pin grid array) package ** System Bus clock rate 100 MHz (E-models), 133 MHz (EB models) ** Slot 1, Socket 370 ** Family 6 model 8 ** Variants *** 500 MHz (100 MHz bus clock rate) *** 533 MHz *** 550 MHz (100 MHz bus clock rate) *** 600 MHz *** 600 MHz (100 MHz bus clock rate) *** 650 MHz (100 MHz bus clock rate) introduced October 25, 1999 *** 667 MHz introduced October 25, 1999 *** 700 MHz (100 MHz bus clock rate) introduced October 25, 1999 *** 733 MHz introduced October 25, 1999 *** 750, 800 MHz (100 MHz bus clock rate) introduced December 20, 1999 *** 850 MHz (100 MHz bus clock rate) introduced March 20, 2000 *** 866 MHz introduced March 20, 2000 *** 933 MHz introduced May 24, 2000 *** 1000 MHz introduced March 8, 2000 (not widely available at time of release) *** 1100 MHz *** 1133 MHz (first version recalled, later re-released) *** 400, 450, 500 MHz (Mobile) introduced October 25, 1999 *** 600, 650 MHz (Mobile) introduced January 18, 2000 *** 700 MHz (Mobile) introduced April 24, 2000 *** 750 MHz (Mobile) introduced June 19, 2000 *** 800, 850 MHz (Mobile) introduced September 25, 2000 *** 900, 1000 MHz (Mobile) introduced March 19, 2001 * '''Tualatin''' – [[130 nanometer|0.13 μm process technology]] ** Introduced July 2001 ** 28.1 million transistors ** 32 KB (32 × 1024 B) L1 cache ** 256 KB or 512 KB Advanced Transfer L2 cache (integrated) ** 370-pin [[FC-PGA2]] (flip-chip pin grid array) package ** 133 MHz system bus clock rate ** Socket 370 ** Family 6 model 11 ** Variants *** 1133 MHz (256 KB L2) *** 1133 MHz (512 KB L2) *** 1200 MHz *** 1266 MHz (512 KB L2) *** 1333 MHz *** 1400 MHz (512 KB L2)
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