Editing X86 (section)

===Floating point and SIMD===
A dedicated [[floating-point unit|floating-point processor]] with 80-bit internal registers, the [[Intel 8087|8087]], was developed for the original [[8086]]. This microprocessor subsequently developed into the extended [[80387]], and later processors incorporated a [[backward compatible]] version of this functionality on the same microprocessor as the main processor. In addition to this, modern x86 designs also contain a [[Single instruction, multiple data|SIMD]]-unit (see [[Streaming SIMD Extensions|SSE]] below) where instructions can work in parallel on (one or two) 128-bit words, each containing two or four [[floating-point arithmetic|floating-point number]]s (each 64 or 32&nbsp;bits wide respectively), or alternatively, 2, 4, 8 or 16 integers (each 64, 32, 16 or 8&nbsp;bits wide respectively).

The presence of wide SIMD registers means that existing x86 processors can load or store up to 128&nbsp;bits of memory data in a single instruction and also perform bitwise operations (although not integer arithmetic{{Efn|That is because integer arithmetic generates carry between subsequent bits (unlike simple bitwise operations).}}) on full 128-bits quantities in parallel. Intel's [[Sandy Bridge]] processors added the [[Advanced Vector Extensions]] (AVX) instructions, widening the SIMD registers to 256 bits. The Intel Initial Many Core Instructions implemented by the Knights Corner [[Xeon Phi]] processors, and the [[AVX-512]] instructions implemented by the Knights Landing Xeon Phi processors and by [[Skylake (microarchitecture)#High-end desktop processors (Skylake-X)|Skylake-X]] processors, use 512-bit wide SIMD registers.
<!-- The fact that "MOV" has been extended to cope with 128-bit words does not make the 128-bit SSE registers general purpose. The bitwise instructions extended for 128-bit SSE registers and memory locations is just SSE/SIMD, plain and simple. The fact that 128-bit registers can be pushed and popped to/from the stack with "normal instructions" is nothing more remarkable than the "MOV" mentioned above (although very useful). Only 128-bit SSE words (not 128-bit integers or addresses) are enabled by the single-instruction-single-data core. What opcodes are used are irrelevant here.-->