Jump to content
Main menu
Main menu
move to sidebar
hide
Navigation
Main page
Recent changes
Random page
Help about MediaWiki
Special pages
Niidae Wiki
Search
Search
Appearance
Create account
Log in
Personal tools
Create account
Log in
Pages for logged out editors
learn more
Contributions
Talk
Editing
Transputer
(section)
Page
Discussion
English
Read
Edit
View history
Tools
Tools
move to sidebar
hide
Actions
Read
Edit
View history
General
What links here
Related changes
Page information
Appearance
move to sidebar
hide
Warning:
You are not logged in. Your IP address will be publicly visible if you make any edits. If you
log in
or
create an account
, your edits will be attributed to your username, along with other benefits.
Anti-spam check. Do
not
fill this in!
=== Instruction set === To include all this function on one chip, the transputer's core logic was simpler than most CPUs. While some have called it [[reduced instruction set computer]] (RISC) due to its rather sparse nature, and because that was then a desirable marketing [[buzzword]], it was heavily [[microcode]]d, had a limited register set, and complex memory-to-memory instructions, all of which place it firmly in the [[complex instruction set computer|CISC]] camp. Unlike register-heavy [[Load/store architecture|load/store RISC]] CPUs, the transputer had only three data registers, which behaved as a stack. In addition a workspace pointer pointed to a conventional memory stack, easily accessible via the instructions <code>Load Local</code> and <code>Store Local</code>. This allowed for very fast [[context switch]]ing by simply changing the workspace pointer to the memory used by another process (a method used in a number of contemporary designs, such as the [[TMS9900]]). The three register stack contents were not preserved past certain instructions, like Jump, when the transputer could do a context switch. The transputer instruction set consisted of 8-bit instructions assembled from [[opcode]] and [[operand]] [[nibble]]s. The ''upper'' nibble contained the 16 possible primary instruction codes, making it one of the very few commercialized [[minimal instruction set computer]]s. The ''lower'' nibble contained the one immediate constant operand, commonly used as an offset relative to the workspace (memory stack) pointer. Two [[prefix]] instructions allowed construction of larger constants by prepending their lower nibbles to the operands of following instructions. Further instructions were supported via the instruction code ''Operate'' (<code>Opr</code>), which decoded the constant operand as an extended zero-operand opcode, providing for almost endless and easy instruction set expansion as newer implementations of the transputer were introduced. The 16 'primary' one-operand instructions were: {| class="wikitable" |- ! Mnemonic ! Description |- |J |Jump β add immediate operand to instruction pointer |- |LDLP |Load local pointer β load a workspace-relative pointer onto the top of the register stack |- |PFIX |Prefix β general way to increase lower nibble of following primary instruction |- |LDNL |Load non-local β load a value offset from address at top of stack |- |LDC |Load constant β load constant operand onto the top of the register stack |- |LDNLP |Load non-local pointer β load address, offset from top of stack |- |NFIX |Negative prefix β general way to negate (and possibly increase) lower nibble |- |LDL |Load local β load value offset from workspace |- |ADC |Add constant β add constant operand to top of register stack |- |CALL |Subroutine call β push instruction pointer and jump |- |CJ |Conditional jump β depending on value at top of register stack |- |AJW |Adjust workspace β add operand to workspace pointer |- |EQC |Equals constant β test if top of register stack equals constant operand |- |STL |Store local β store at constant offset from workspace |- |STNL |Store non-local β store at address offset from top of stack |- |OPR |Operate β general way to extend instruction set |} All these instructions take a constant, representing an offset or an arithmetic constant. If this constant was less than 16, all these instructions coded to one byte. The first 16 'secondary' zero-operand instructions (using the OPR primary instruction) were: {| class="wikitable" |- ! Mnemonic ! Description |- |REV |Reverse β swap two top items of register stack |- |LB |Load byte |- |BSUB |Byte subscript |- |ENDP |End process |- |DIFF |Difference |- |ADD |Add |- |GCALL |General call β swap top of stack and instruction pointer |- |IN |Input β receive message |- |PROD |Product |- |GT |Greater than β the only comparison instruction |- |WSUB |Word subscript |- |OUT |Output β send message |- |SUB |Subtract |- |STARTP |Start process |- |OUTBYTE |Output byte β send one-byte message |- |OUTWORD |Output word β send one-word message |}
Summary:
Please note that all contributions to Niidae Wiki may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see
Encyclopedia:Copyrights
for details).
Do not submit copyrighted work without permission!
Cancel
Editing help
(opens in new window)
Search
Search
Editing
Transputer
(section)
Add topic