Editing Synchronous dynamic random-access memory (section)

=== Commands ===
The SDR SDRAM commands are defined as follows:

{| class="wikitable" style="text-align:center"
! {{overline|CS}} || {{overline|RAS}} || {{overline|CAS}} || {{overline|WE}} || BA''n'' || A10 || A''n'' || Command
|-
|bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x  ||bgcolor=lightgrey| x  ||bgcolor=lightgrey| x ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Command inhibit (no operation)
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| No operation
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Burst terminate: stop a burst read or burst write in progress
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   || bank    ||bgcolor=#ccffcc| L   || column ||align="left"| Read: read a burst of data from the currently active row
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   || bank    ||bgcolor=#ffcccc| H   || column ||align="left"| Read with auto precharge: as above, and precharge (close row) when done
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ccffcc| L   || column ||align="left"| Write: write a burst of data to the currently active row
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ffcccc| H   || column ||align="left"| Write with auto precharge: as above, and precharge (close row) when done
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ffcccc| H   || bank  ||colspan="2"| row ||align="left"| Active (activate): open a row for read and write commands
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   || bank    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x      ||align="left"| Precharge: deactivate (close) the current row of selected bank
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H    ||bgcolor=#ccffcc| L   ||bgcolor=lightgrey| x       ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x      ||align="left"| Precharge all: deactivate (close) the current row of all banks
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L    ||bgcolor=#ffcccc| H   ||bgcolor=lightgrey| x       ||bgcolor=lightgrey| x   ||bgcolor=lightgrey| x      ||align="left"| Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged.
|-
|bgcolor=#ccffcc| L   ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L    ||bgcolor=#ccffcc| L   || 0 0  ||colspan="2"| mode ||align="left"| Load mode register: A0 through A9 are loaded to configure the DRAM chip.<br/>The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)
|}

All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being:
* Additional address bits to support larger devices
* Additional bank select bits
* Wider mode registers (DDR2 and up use 13 bits, A0–A12)
* Additional extended mode registers (selected by the bank address bits)
* DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"
* DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer
* [[DDR4#Command encoding|DDR4 changes the encoding]] of the activate command. A new signal {{overline|ACT}} controls it, during which the other control lines are used as row address bits 16, 15 and 14. When {{overline|ACT}} is high, other commands are the same as above.