Editing SuperH (section)

===J Core===
{{Distinguish|Samsung Galaxy J2 Core}}
The last of the SH-2 patents expired in 2014. At [[LinuxCon]] Japan 2015, j-core developers presented a [[clean room design|cleanroom reimplemention]] of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired [[trademarks]]).<ref name="lwn">{{cite web|url=http://lwn.net/Articles/647636|title=Resurrecting the SuperH architecture|author=Nathan Willis|date=June 10, 2015|publisher=[[LWN.net]]}}</ref><ref name="0pf_jcore">{{cite web|url=http://j-core.org|title=J Cores|publisher=j-core|access-date=April 27, 2016|url-status=dead|archive-url=https://web.archive.org/web/20160511092659/http://j-core.org/|archive-date=May 11, 2016}}</ref> Subsequently, a design walkthrough was presented at ELC 2016.<ref>{{cite web |url=http://j-core.org/talks/ELC-2016.pdf |archive-url=https://web.archive.org/web/20160617085346/http://j-core.org/talks/ELC-2016.pdf |archive-date=2016-06-17 |url-status=live |title=j-core Design Walkthrough}}</ref>

The [[open-source license|open source]] [[Berkeley Software Distribution|BSD]]-licensed [[VHDL]] code for the J2 core has been proven on [[Xilinx]] [[FPGA]]s and on [[ASIC]]s manufactured on [[TSMC]]'s [[180 nm]] process, and is capable of booting [[μClinux]].<ref name="lwn"/>  J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine-generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA.  Additional instructions are easy to add.  J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support.  Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire<!--expired?--> in 2016–2017.<ref name="lwn"/>{{needs update|date=June 2022}}

Several features of SuperH have been cited as motivations for designing new cores based on this architecture:<ref name="lwn"/>

* High [[code density]] compared to other 32-bit [[RISC]] [[instruction set architecture|ISA]]s such as [[ARM architecture|ARM]] or [[MIPS architecture|MIPS]]<ref name="weaver2015">{{cite news|author=V.M. Weaver|title=Exploring the Limits of Code Density (Tech Report with Newest Results)|date=17 March 2015|url=http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf |archive-url=https://web.archive.org/web/20150713143728/http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf |archive-date=2015-07-13 |url-status=live}}</ref> important for cache and memory bandwidth performance
* Existing [[C compiler|compiler]] and [[operating system]] support ([[Linux]], [[Windows Embedded]], [[QNX]]<ref name="0pf_jcore"/>)
* Extremely low ASIC [[semiconductor fabrication|fabrication]] costs now that the patents are expiring (around {{USD|0.03}} for a dual-core J2 core on TSMC's 180&nbsp;nm process).
* Patent- and royalty-free (BSD-licensed) implementation
* Full and vibrant community support
* Availability of low cost hardware development platform for zero cost FPGA tools
* CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation
* Clean, modern design with open source design, generation, simulation and verification environment