Editing Motorola 68020 (section)

=== Improvements over the 68010 ===
{{Unreferenced section|date=November 2024}}

The 68020 has a 32-bit [[arithmetic logic unit]] (ALU), 32-bit external data and address buses.<ref>{{Cite web |last=alldatasheet.com |title=MC68020 PDF |url=https://www.alldatasheet.com/datasheet-pdf/view/112181/MOTOROLA/MC68020.html |access-date=2025-02-27 |website=www.alldatasheet.com |language=en}}</ref>  It adds extra instructions and additional addressing modes. The 68020 (and 68030) has a proper three-stage pipeline. Though the 68010 had a "loop mode", which sped loops through what was effectively a tiny instruction cache, it held only two short instructions and was thus little used. The 68020 replaced this with a proper instruction cache of 256 bytes, the first 68k series processor to feature true on-chip cache memory.
 
The previous 68000 and 68010 processors could only access word (16-bit) and long word (32-bit) data in memory if it were word-aligned (located at an even address). The 68020 has no alignment restrictions on data access. Naturally, unaligned accesses are slower than aligned accesses because they required an extra memory access.

The 68020 has a small 256-byte direct-mapped instruction cache, arranged as 64 four-byte entries. Although small, it still made a significant difference in the performance of many applications. The resulting decrease in bus traffic was particularly important in systems relying heavily on [[Direct memory access|DMA]].