Editing Magnetic-core memory (section)

===Reading and writing===
[[File:Ringkernspeicher hysteresekurven.agr.svg|thumb|right|Diagram of the [[Magnetic hysteresis|hysteresis]] curve for a magnetic memory core during a read operation. Sense line current pulse is high ("1") or low ("0") depending on original magnetization state of the core.]]

The access time plus the time to rewrite is the '''memory cycle time'''.

====Reading====
To read a bit of core memory, the circuitry tries to flip the bit to the polarity assigned to the 0 state, by driving the selected X and Y lines that intersect at that core.

* If the bit was already 0, the physical state of the core is unaffected.
* If the bit was previously 1, then the core changes magnetic polarity. This change, after a delay, induces a voltage pulse into the Sense line.

The detection of such a pulse means that the bit had most recently contained a 1. Absence of the pulse means that the bit had contained a 0. The delay in sensing the voltage pulse is called the '''access time''' of the core memory.

Following any such read, the bit contains a 0. This illustrates why a core memory access is called a ''destructive read'': Any operation that reads the contents of a core erases those contents, and they must immediately be recreated.

====Writing====
To write a bit of core memory, the circuitry assumes there has been a read operation and the bit is in the 0 state.

* To write a 1 bit, the selected X and Y lines are driven, with current in the opposite direction as for the read operation. As with the read, the core at the intersection of the X and Y lines changes magnetic polarity.
* To write a 0 bit, two methods can be applied. The first one is the same as reading process with current in the original direction. The second has reversed logic. To write a 0 bit, in other words, is to inhibit the writing of a 1 bit. The same amount of current is also sent through the Inhibit line. This reduces the net current flowing through the respective core to half the select current, inhibiting change of polarity.

====Combined sense and inhibit====
The Sense wire is used only during the read, and the Inhibit wire is used only during the write. For this reason, later core systems combined the two into a single wire, and used circuitry in the memory controller to switch the function of the wire.

However, when Sense wire crosses too many cores, the half select current can also induce a considerable voltage across the whole line due to the superposition of the voltage at each single core. This potential risk of "misread" limits the minimum number of Sense wires.

Increasing Sense wires also requires more decode circuitry.

====Combined read and write with modify====
Core memory controllers were designed so that every read was followed immediately by a write (because the read forced all bits to 0, and because the write assumed this had happened). [[Instruction set]]s were designed to take advantage of this.

For example, a value in memory could be read and modified almost as quickly as it could be read and written. In the [[PDP-6]], the <code>AOS*</code> (or <code>SOS*</code>) instructions incremented (or decremented) the value between the read phase and the write phase of a single memory cycle (perhaps signaling the memory controller to pause briefly in the middle of the cycle). This might be twice as fast as the process of obtaining the value with a read-write cycle, incrementing (or decrementing) the value in some processor register, and then writing the new value with another read-write cycle.