Editing Intel 8086 (section)

===Registers and instruction===
{| class="infobox" style="font-size:88%;width:38em;"
|-
|+ Intel 8086 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="21" | '''Main registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| AH
| style="text-align:center;" colspan="8"| AL
| style="background:white; color:black;"| '''[[Accumulator (computing)|AX]]''' (primary accumulator)
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="8"| BH
| style="text-align:center;" colspan="8"| BL
| style="background:white; color:black;"| '''BX''' (base, accumulator)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| CH
| style="text-align:center;" colspan="8"| CL
| style="background:white; color:black;"| '''CX''' (counter, accumulator)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| DH
| style="text-align:center;" colspan="8"| DL
| style="background:white; color:black;"| '''DX''' (accumulator, extended acc)
|-
|colspan="21" | '''Index registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Index register|SI]]
| style="background:white; color:black;"| '''S'''ource '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| DI
| style="background:white; color:black;"| '''D'''estination '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| BP
| style="background:white; color:black;"| '''B'''ase '''P'''ointer
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Stack register|SP]]
| style="background:white; color:black;"| '''S'''tack '''P'''ointer
|-
|colspan="21" | '''Program counter''' <br />
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Program counter|IP]]
| style="background:white; color:black;"| '''I'''nstruction '''P'''ointer
|-
|colspan="21" | '''Segment registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| CS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''C'''ode '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| DS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''D'''ata '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| ES
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''E'''xtra '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| SS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''S'''tack '''S'''egment
|-
|colspan="21" | '''Status register'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| [[Overflow flag|O]]
| style="text-align:center;"| [[Direction flag|D]]
| style="text-align:center;"| [[IF (x86 flag)|I]]
| style="text-align:center;"| [[Trap flag|T]]
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Adjust flag|A]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Parity flag|P]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | Flags
|}
|}
The 8086 has eight more-or-less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.

Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time.

The degree of generality of most registers is much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary [[minicomputer]]s and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the [[PDP-11]], [[VAX]], [[68000]], [[32016]], etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6800|6800]], [[6809]], [[Intel 8085|8085]], [[MCS-48]], [[Intel 8051|8051]], and other contemporary accumulator-based machines, it is significantly easier to construct an efficient [[code generation (compiler)|code generator]] for the 8086 architecture.

Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and [[PL/M]]; some of the more useful instructions are <code>'''push''' ''mem-op''</code>, and '''ret''' ''size'', supporting the "Pascal [[calling convention]]" directly. (Several others, such as <code>'''push'''&nbsp;''immed''</code> and <code>'''enter'''</code>, were added in the subsequent 80186, 80286, and 80386 processors.)

A 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported in [[computer hardware|hardware]]; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256&nbsp;[[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address (computing)|return address]]es.

The 8086 has 64&nbsp;K of 8-bit (or alternatively 32&nbsp;K of 16-bit word) [[I/O port]] space.