Editing Hitachi 6309 (section)

===Additional instructions===
Most of the new instructions are modifications of existing instructions to handle the existence of the additional registers, such as load, store, add, and the like. Genuine 6309 additions include inter-register arithmetic, block transfers, hardware division, and bit-level manipulations. Further, 16 bit registers D and W can be target of 16 bit arithmetic with carry and 16 bit shift and rotate operations. On 6809, these operations are limited to 8 bit operands.

Despite the user-friendliness of the additional instructions, analysis by 6809 programming gurus{{who|date=May 2016}} indicates that many of the new instructions are actually slower than the equivalent 6809 code, especially in tight loops.{{citation needed|date=May 2016}} Careful analysis should be done to ensure that the programmer uses the most efficient code for the particular application.

Most of new instructions use prefix opcode and that makes them slower by one cycle when compared to similar 6809 instruction. On other side, 6309 native mode executes many instructions faster by one or more cycles. Here is a timing comparison of an 8 bit LD instruction for 'A' register and 'E' register on 6809 and 6309:
{| class="wikitable"
|-
! scope="col" |instruction
! scope="col" |6809
! scope="col" |6309 emulation mode
! scope="col" |6309 native mode
|-
|LDA immediate
|2 cycles
|2 cycles
|2 cycles
|-
|LDE immediate
|n/a
|3 cycles
|3 cycles
|-
|LDA direct
|4 cycles
|4 cycles
|3 cycles
|-
|LDE direct
|n/a
|5 cycles
|4 cycles
|-
|LDA indexed
|4+ cycles
|4+ cycles
|4+ cycles
|-
|LDE indexed
|n/a
|5+ cycles
|5+ cycles
|-
|LDA extended
|5 cycles
|5 cycles
|4 cycles
|-
|LDE extended
|n/a
|6 cycles
|5 cycles
|}

Also inter-register operations and new 16 bit operations are somewhat mixed bag. Depending on addressing mode and 6309 mode, equivalent 6809 code can be faster. For illustration, let us look on timing of exclusive or instruction.

{| class="wikitable"
|-
! scope="col" |instruction
! scope="col" |6809
! scope="col" |6309 emulation mode
! scope="col" |6309 native mode
|-
|EORA immediate
|2 cycles
|2 cycles
|2 cycles
|-
|EORD immediate
|n/a
|5 cycles
|4 cycles
|-
|EORA direct
|4 cycles
|4 cycles
|3 cycles
|-
|EORD direct
|n/a
|7 cycles
|5 cycles
|-
|EORA indexed
|4+ cycles
|4+ cycles
|4+ cycles
|-
|EORD indexed
|n/a
|7+ cycles
|6+ cycles
|-
|EORA extended
|5 cycles
|5 cycles
|4 cycles
|-
|EORD extended
|n/a
|8 cycles
|6 cycles
|-
|EORR inter-register
|n/a
|4 cycles
|4 cycles
|} 

As table above indicates, exclusive or of 16 bit register D with immediate parameter can be replaced by two 8 bit instructions EORA imm, EORB imm and it will execute faster when 6309 runs in emulation mode. Though one should realize that sequence of 8 bit instructions EORA imm, EORB imm is not exact equivalent of 16 bit EORD imm instruction as condition code CC register is set according result of 8 bit operation in first case and according result of 16 bit operation in second case.    

Similar issue is with inter-register EORR instruction. It accepts both 8 bit and 16 bit operands and it always executes within 4 cycles. However, for 8 bit operands, it is faster to use EORA imm or EORB imm instructions when appropriate. Further, when 6309 is running in native mode, instructions EORA direct, EORB direct take only 3 cycles, one cycle less than inter-register operation.