Editing Field-programmable gate array (section)

=== Logic blocks ===
{{Main|Logic block}}
[[File:FPGA cell example.png|thumb|Simplified example illustration of a logic cell (LUT&nbsp;&ndash; [[lookup table]], FA&nbsp;&ndash; [[full adder]], DFF&nbsp;&ndash; [[D-type flip-flop]])]]

The most common FPGA architecture consists of an array of [[logic block]]s called configurable logic blocks (CLBs) or logic array blocks (LABs) (depending on vendor), [[I/O address|I/O pads]], and routing channels.<ref name="FPGA" /> Generally, all the routing channels have the same width (number of signals). Multiple I/O pads may fit into the height of one row or the width of one column in the array.

"An application circuit must be mapped into an FPGA with adequate resources. While the number of logic blocks and I/Os required is easily determined from the design, the number of routing channels needed may vary considerably even among designs with the same amount of logic. For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count. Since unused routing channels increase the cost (and decrease the performance) of the FPGA without providing any benefit, FPGA manufacturers try to provide just enough channels so that most designs that will fit in terms of [[Lookup table#Hardware LUTs|lookup tables]] (LUTs) and I/Os can be [[Routing (electronic design automation)|routed]]. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs."<ref>{{Cite journal |last1=M.b |first1=Swami |last2=V.p |first2=Pawar |date=2014-07-31 |title=VLSI DESIGN: A NEW APPROACH |url=https://bioinfopublication.org/pages/article.php?id=BIA0002301 |journal=Journal of Intelligence Systems |language=En |volume=4 |issue=1 |pages=60–63 |issn=2229-7057}}</ref>

In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, a [[Adder (electronics)|full adder]] (FA) and a [[D-type flip-flop]]. The LUT might be split into two 3-input LUTs. In ''normal mode'' those are combined into a 4-input LUT through the first [[multiplexer]] (mux). In ''arithmetic'' mode, their outputs are fed to the adder. The selection of mode is programmed into the second mux. The output can be either [[Synchronous circuit|synchronous]] or [[Asynchronous circuit|asynchronous]], depending on the programming of the third mux. In practice, the entire adder or parts of it are [[Shannon expansion|stored as functions]] into the LUTs in order to save [[Circuit utilization|space]].<ref>[http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf 2. CycloneII Architecture]. Altera. February 2007</ref><ref>{{cite web |url=http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf |title=Documentation: Stratix IV Devices |publisher=Altera.com |date=2008-06-11 |access-date=2013-05-01 |archive-url=https://web.archive.org/web/20110926214034/http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf |archive-date=2011-09-26 |url-status=dead}}</ref><ref>[http://www.xilinx.com/support/documentation/user_guides/ug070.pdf Virtex-4 FPGA User Guide] (December 1st, 2008). Xilinx, Inc.</ref>