Editing DEC Alpha (section)

===Condition codes===
The Alpha does not have [[Status register|condition code]]s for integer instructions<ref>{{cite web
|title=MIPS Instructions
|url=http://eas.uccs.edu/~cwang/ECE4480_sp_16/ch2(3rdEdition).PPT
|quote=DEC Alpha ... , no integer condition code.
}}{{Dead link|date=February 2022 |bot=InternetArchiveBot |fix-attempted=yes}}</ref> to remove a potential bottleneck at the condition status register. Instructions resulting in an overflow, such as adding two numbers whose result does not fit in 64 bits, write the 32 or 64 [[least significant bit]]s to the destination register. The carry is generated by performing an unsigned compare on the result with either operand to see if the result is smaller than either operand. If the test was true, the value one is written to the least significant bit of the destination register to indicate the condition.