Editing CMOS (section)

=== Example: NAND gate in physical layout ===
[[File:CMOS NAND Layout.svg|thumb|upright|The [[physical layout]] of a NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent [[latchup]]. ]]
[[File:CMOS fabrication process.svg|thumb|upright|Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. In step 1, [[silicon dioxide]] layers are formed initially through [[thermal oxidation]] Note: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.]]

This example shows a [[Logical NAND|NAND]] logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a [[Extrinsic semiconductor#P-type semiconductors|P-type]] substrate. The [[polysilicon]], diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the [[NAND gate|NAND]] (illustrated in green color) are in polysilicon. The transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The [[physical layout]] example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate while the P device is manufactured in an [[Extrinsic semiconductor#N-type semiconductors|N-type]] well (n-well). A P-type substrate "tap" is connected to V<sub>SS</sub> and an N-type n-well tap is connected to V<sub>DD</sub> to prevent [[latchup]].

[[Image:Cmos impurity profile-en.svg|center|thumbnail|500px|Cross section of two transistors in a CMOS gate, in an N-well CMOS process]]