Editing Analog-to-digital converter (section)

===Jitter===<!--[[Sampling (signal processing)]] links here-->
When digitizing a sine wave <math>x(t)=A \sin{(2 \pi f_0 t)}</math>, the use of a non-ideal sampling clock will result in some uncertainty in when samples are recorded. Provided that the actual sampling time uncertainty due to clock [[jitter]] is <math>\Delta t</math>, the error caused by this phenomenon can be estimated as <math>E_{ap} \le |x'(t) \Delta t| \le 2A \pi f_0 \Delta t</math>.  This will result in additional recorded noise that will reduce the [[effective number of bits]] (ENOB) below that predicted by [[quantization error]] alone. The error is zero for DC, small at low frequencies, but significant with signals of high amplitude and high frequency. The effect of jitter on performance can be compared to quantization error: <math>\Delta t < \frac{1}{2^q \pi f_0}</math>, where q is the number of ADC bits.{{citation needed|date=February 2019}}

{| class="wikitable" style="margin: 1em auto;"
|-
! rowspan="2" | Output size <br />(bits) || colspan="7" | Signal Frequency
|-
! 1&nbsp;Hz||1&nbsp;kHz || 10&nbsp;kHz || 1&nbsp;MHz || 10&nbsp;MHz || 100&nbsp;MHz || 1&nbsp;GHz
|- style="text-align:right;" 
|| 8 || style="text-align:right;"| 1,243&nbsp;μs || style="text-align:right;"| 1.24&nbsp;μs || style="text-align:right;"| 124 ns || style="text-align:right;"| 1.24 ns || style="text-align:right;"| 124 ps || style="text-align:right;"| 12.4 ps || style="text-align:right;"| 1.24 ps
|- style="text-align:right;" 
|| 10 || style="text-align:right;"| 311&nbsp;μs || style="text-align:right;"| 311 ns || style="text-align:right;"| 31.1&nbsp;ns || style="text-align:right;"| 311&nbsp;ps || style="text-align:right;"| 31.1&nbsp;ps || style="text-align:right;"| 3.11&nbsp;ps || style="text-align:right;"| 0.31&nbsp;ps
|- style="text-align:right;" 
|| 12 || style="text-align:right;"| 77.7&nbsp;μs || style="text-align:right;"| 77.7&nbsp;ns || style="text-align:right;"| 7.77&nbsp;ns || style="text-align:right;"| 77.7&nbsp;ps || style="text-align:right;"| 7.77&nbsp;ps || style="text-align:right;"| 0.78&nbsp;ps || style="text-align:right;"| 0.08&nbsp;ps (77.7&nbsp;fs)
|- style="text-align:right;" 
|| 14 || style="text-align:right;"| 19.4&nbsp;μs || style="text-align:right;"| 19.4&nbsp;ns || style="text-align:right;"| 1.94&nbsp;ns || style="text-align:right;"| 19.4&nbsp;ps || style="text-align:right;"| 1.94&nbsp;ps || style="text-align:right;"| 0.19&nbsp;ps || style="text-align:right;"| 0.02&nbsp;ps (19.4&nbsp;fs)
|-
| style="text-align:right;"| 16 || style="text-align:right;"| 4.86&nbsp;μs || style="text-align:right;"| 4.86&nbsp;ns || style="text-align:right;"| 486&nbsp;ps || style="text-align:right;"| 4.86&nbsp;ps || style="text-align:right;"| 0.49&nbsp;ps || style="text-align:right;"| 0.05&nbsp;ps (48.5&nbsp;fs)|| style="text-align:center;"| –
|-
| style="text-align:right;"| 18 || style="text-align:right;"| 1.21&nbsp;μs || style="text-align:right;"| 1.21&nbsp;ns || style="text-align:right;"| 121&nbsp;ps || style="text-align:right;"| 1.21&nbsp;ps || style="text-align:right;"| 0.12&nbsp;ps || style="text-align:center;"| – || style="text-align:center;"| –
|-
| style="text-align:right;"| 20 || style="text-align:right;"| 304&nbsp;ns || style="text-align:right;"| 304&nbsp;ps || style="text-align:right;"| 30.4&nbsp;ps || style="text-align:right;"| 0.30&nbsp;ps (303.56&nbsp;fs) || style="text-align:center;"| 0.03&nbsp;ps (30.3&nbsp;fs)|| style="text-align:center;"| – || style="text-align:center;"| –
|-
| style="text-align:right;"| 24 || style="text-align:right;"| 18.9&nbsp;ns || style="text-align:right;"| 18.9&nbsp;ps || style="text-align:right;"| 1.89&nbsp;ps || style="text-align:right;"| 0.019&nbsp;ps (18.9&nbsp;fs) || style="text-align:center;"| - || style="text-align:center;"| – || style="text-align:center;"| –
|-
|}

Clock jitter is caused by [[phase noise]].<ref>{{citation |url=http://www.maxim-ic.com/appnotes.cfm/an_pk/800/ |title=Maxim App 800: Design a Low-Jitter Clock for High-Speed Data Converters |website=maxim-ic.com |date=July 17, 2002}}</ref><ref>{{cite web | title = Jitter effects on Analog to Digital and Digital to Analog Converters | url = http://www.thewelltemperedcomputer.com/Lib/Troisi.pdf | access-date = 19 August 2012}}</ref> The resolution of ADCs with a [[digitization]] bandwidth between 1&nbsp;MHz and 1&nbsp;GHz is limited by jitter.<ref>{{cite journal |doi=10.1016/j.csi.2005.12.005 |title=The effects of aperture jitter and clock jitter in wideband ADCs |last1=Löhning |first1=Michael |last2=Fettweis |first2=Gerhard |year=2007 |journal=Computer Standards & Interfaces Archive |volume =29 |issue=1 |pages=11–18 |citeseerx=10.1.1.3.9217}}</ref> For lower bandwidth conversions such as when sampling audio signals at 44.1&nbsp;kHz, clock jitter has a less significant impact on performance.<ref>{{citation |last1=Redmayne |first1=Derek |last2=Steer |first2=Alison |date=8 December 2008 |url=http://www.eetimes.com/design/automotive-design/4010074/Understanding-the-effect-of-clock-jitter-on-high-speed-ADCs-Part-1-of-2- |title=Understanding the effect of clock jitter on high-speed ADCs |website=eetimes.com}}</ref>