Editing AVR microcontrollers (section)

==== Internal registers ====
In the tinyAVR and megaAVR variants of the [[Atmel AVR instruction set|AVR architecture]], the working registers are mapped in as the first 32 data memory addresses (0000<sub>16</sub>–001F<sub>16</sub>), followed by 64 I/O registers (0020<sub>16</sub>–005F<sub>16</sub>). In devices with many peripherals, these registers are followed by 160 “extended I/O” registers, only accessible as [[memory-mapped I/O]] (0060<sub>16</sub>–00FF<sub>16</sub>).

Actual SRAM starts after these register sections, at address 0060<sub>16</sub> or, in devices with "extended I/O", at 0100<sub>16</sub>.

Even though there are separate addressing schemes and optimized opcodes for accessing the register file and the first 64 I/O registers, all can also be addressed and manipulated as if they were in SRAM.

The very smallest of the tinyAVR variants use a reduced architecture with only 16 registers (r0 through r15 are omitted) which are not addressable as memory locations. I/O memory begins at address 0000<sub>16</sub>, followed by SRAM. In addition, these devices have slight deviations from the standard AVR instruction set. Most notably, the direct load/store instructions (LDS/STS) have been reduced from 2 words (32 bits) to 1 word (16 bits), limiting the total direct addressable memory (the sum of both I/O and SRAM) to 128 bytes. Conversely, the indirect load instruction's (LD) 16-bit address space is expanded to also include non-volatile memory such as Flash and configuration bits; therefore, the Load Program Memory (LPM) instruction is unnecessary and omitted. (For detailed info, see [[Atmel AVR instruction set]].)

In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (0000<sub>16</sub>–0FFF<sub>16</sub>). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space, which can be used optionally for mapping the internal EEPROM to the data address space (1000<sub>16</sub>–1FFF<sub>16</sub>). The actual SRAM is located after these ranges, starting at 2000<sub>16</sub>.