Editing VHDL (section)

==Advantages==
The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a [[concurrent system]]. VHDL is a [[Dataflow programming|dataflow language]] in which every statement is considered for execution simultaneously, unlike procedural computing languages such as BASIC, C, and assembly language, where a sequence of statements is run sequentially one instruction at a time.

A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure).

A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base; for example, [[VLSI]] with various technologies.

A big advantage of VHDL compared to original [[Verilog]] is that VHDL has a full [[type system]]. Designers can use the type system to write much more structured code (especially by declaring [[Record (computer science)|record]] types).<ref>{{cite web |url=http://gaisler.com/doc/structdesign.pdf |archive-url=https://ghostarchive.org/archive/20221010/http://gaisler.com/doc/structdesign.pdf |archive-date=2022-10-10 |url-status=live |access-date=15 November 2017 |title=A structured VHDL Design Method |author=Jiri Gaisler}}</ref>