Editing TRS-80 Color Computer (section)

===SAM===
The SAM is a multifunction device that performs the following functions:
* Clock generation and synchronization for the 6809E MPU and 6847 VDG
* Up to 64&nbsp;KB dynamic random access memory (DRAM) control and [[memory refresh|refresh]]
* Device selection based on MPU memory address to determine if the MPU access is to DRAM, ROM, PIA, etc.
* Duplication of the VDG address counter to "feed" the VDG the data it is expecting

The SAM was designed to replace numerous small LS/[[Transistor–transistor logic|TTL]] chips into one integrated package. Its main purpose is to control the DRAM but, as outlined above, it integrates several other functions as well. It is connected to a crystal at 4 times the television [[colorburst]] frequency (14.31818&nbsp;MHz for NTSC countries). This is divided by 4 internally and is fed to the VDG for its own internal timing (3.579545&nbsp;MHz for NTSC). The SAM also divides the master clock by 16 (or 8 in certain cases) for the [[two-phase clock|two phase MPU clock]]; in NTSC this is 0.89&nbsp;MHz (or 1.8&nbsp;MHz if divided by 8).

Switching the SAM into 1.8&nbsp;MHz operation gives the CPU the time ordinarily used by the VDG and refresh. As such, the display shows garbage; this mode was seldom used. However, an unusual mode available by the SAM is called the Address Dependent mode, where ROM reads (since they do not use the DRAM) occur at 1.8&nbsp;MHz but regular RAM access occurs at 0.89&nbsp;MHz. In effect, since the BASIC interpreter runs from ROM, putting the machine in this mode would nearly double the performance of a BASIC program while maintaining video display and DRAM refresh. Of course, this would throw off the software timing loops and I/O operations would be affected. Despite this, however, the "high speed [[PEEK and POKE|POKE]]" was used by many CoCo BASIC programs even though it [[overclocking|overclocked]] the hardware in the CoCo, which was only rated for 1&nbsp;MHz operation.

The SAM has no connection to the MPU data bus. As such, it is programmed in a curious manner; its 16-bit configuration register is spread across 32 memory addresses (FFC0-FFDF). Writing even bytes sets that register bit to 0, while writing odd bytes sets it to 1. The value (D7-D0) that is written is ignored.

Due to limitations in 40-pin packaging, the SAM contains a duplicate of the VDG's internal 12-bit address counter. Normally this counter's settings are set to duplicate the VDG's display mode. However, this is not required and results in the creation of some new display modes not possible when the VDG is used in a system alone. Instead of the VDG requesting data from RAM by itself, the VDG is "fed" data by the SAM's internal copy of the VDG address counter. This process is called "Interleaved Direct Memory Access" (IDMA) by Motorola and ensures that the processor and VDG always have full access to this shared memory resource with no wait states or contention.

There are two versions of the SAM. The early one is labeled MC6883 and/or SN74LS783; the later version is labeled SN74LS785. There are some minor timing differences, but the major difference is the support of an 8-bit refresh counter in the 785 version. This allowed for use of inexpensive 16K by 4-bit and certain 64K by 1-bit DRAMs. Some third-party [[bank-switching]] memory upgrades that used 256K DRAMs needed this 8-bit refresh counter to work.