Editing System on a chip (section)

== Structure ==
An SoC consists of hardware [[functional unit]]s, including [[microprocessor]]s that run [[Computer program|software code]], as well as a [[communications subsystem]] to connect, control, direct and interface between these functional modules.

=== Functional components ===
==== Processor cores ====
An SoC must have at least one [[processor core]], but typically an SoC has more than one core. Processor cores can be a [[microcontroller]], [[microprocessor]] (μP),<ref name="Furber ARM">{{Cite book|title=ARM system-on-chip architecture|last=Furber|first=Stephen B.|publisher=Addison-Wesley|year=2000|isbn=0-201-67519-6|location=Harlow, England|oclc=44267964}}</ref> [[digital signal processor]] (DSP) or [[application-specific instruction set processor]] (ASIP) core.<ref name=":1">{{Cite book|title=Pipelined Multiprocessor System-on-Chip for Multimedia|publisher=[[Springer-Verlag|Springer]]|year=2014|isbn=978-3-319-01113-4|oclc=869378184|author=Haris Javaid |author2=Sri Parameswaran }}</ref> ASIPs have [[Instruction set architecture|instruction sets]] that are customized for an [[application domain]] and designed to be more efficient than general-purpose instructions for a specific type of workload. Multiprocessor SoCs have more than one processor core by definition. The [[ARM architecture]] is a common choice for SoC processor cores because some ARM-architecture cores are [[Soft microprocessor|soft processor]]s specified as [[IP core]]s.<ref name="Furber ARM" />

==== Memory ====
{{Further|Computer memory}}
SoCs must have [[semiconductor memory]] blocks to perform their computation, as do [[microcontroller]]s and other [[embedded system]]s. Depending on the application, SoC memory may form a [[memory hierarchy]] and [[cache hierarchy]]. In the mobile computing market, this is common, but in many [[Low-power electronics|low-power]] embedded microcontrollers, this is not necessary. Memory technologies for SoCs include [[read-only memory]] (ROM), [[random-access memory]] (RAM), Electrically Erasable Programmable ROM ([[EEPROM]]) and [[flash memory]].<ref name="Furber ARM" /> As in other computer systems, RAM can be subdivided into relatively faster but more expensive [[Static random-access memory|static RAM]] (SRAM) and the slower but cheaper [[Dynamic random-access memory|dynamic RAM]] (DRAM). When an SoC has a [[Cache (computing)|cache]] hierarchy, SRAM will usually be used to implement [[processor register]]s and cores' [[CPU cache|built-in cache]]s whereas DRAM will be used for [[main memory]]. "Main memory" may be specific to a single processor (which can be [[Multi-core processor|multi-core]]) when the SoC [[Multi-processor system-on-chip|has multiple processors]], in this case it is [[distributed memory]] and must be sent via {{Section link||Intermodule communication|nopage=y}} on-chip to be accessed by a different processor.<ref name=":1" /> For further discussion of multi-processing memory issues, see [[cache coherence]] and [[memory latency]].

==== Interfaces ====
SoCs include external [[Electrical connector|interfaces]], typically for [[communication protocol]]s. These are often based upon industry standards such as [[USB]], [[Ethernet]], [[Universal synchronous and asynchronous receiver-transmitter|USART]], [[Serial Peripheral Interface|SPI]], [[HDMI]], [[I²C]], [[Camera Serial Interface|CSI]], etc. These interfaces will differ according to the intended application. [[Wireless network]]ing protocols such as [[Wi-Fi]], [[Bluetooth]], [[6LoWPAN]] and [[near-field communication]] may also be supported.

When needed, SoCs include [[Analog signal|analog]] interfaces including [[Analog-to-digital converter|analog-to-digital]] and [[digital-to-analog converter]]s, often for [[signal processing]]. These may be able to interface with different types of [[sensor]]s or [[actuator]]s, including [[smart transducer]]s. They may interface with application-specific [[modularity|modules]] or shields.<ref group="nb">In [[embedded system]]s, "shields" are analogous to [[expansion card]]s for [[Personal computer|PCs]]. They often fit over a [[microcontroller]] such as an [[Arduino]] or [[single-board computer]] such as the [[Raspberry Pi]] and function as [[peripheral]]s for the device.</ref> Or they may be internal to the SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing.

==== Digital signal processors ====
[[Digital signal processor]] (DSP) cores are often included on SoCs. They perform [[signal processing]] operations in SoCs for [[sensor]]s, [[actuator]]s, [[data collection]], [[data analysis]] and multimedia processing. DSP cores typically feature [[very long instruction word]] (VLIW) and [[single instruction, multiple data]] (SIMD) [[instruction set architecture]]s, and are therefore highly amenable to exploiting [[instruction-level parallelism]] through [[Parallel processing (DSP implementation)|parallel processing]] and [[superscalar execution]].<ref name=":1" />{{Rp|4}}  SP cores most often feature application-specific instructions, and as such are typically [[application-specific instruction set processor]]s (ASIP). Such application-specific instructions correspond to dedicated hardware [[functional unit]]s that compute those instructions.

Typical DSP instructions include [[Multiply–accumulate operation|multiply-accumulate]], [[Fast Fourier transform]], [[Fused multiply-accumulate|fused multiply-add]], and [[convolution]]s.

==== Other ====
As with other computer systems, SoCs require [[Clock generator|timing sources]] to generate [[clock signal]]s, control execution of SoC functions and provide time context to [[signal processing]] applications of the SoC, if needed. Popular time sources are [[crystal oscillators]] and [[phase-locked loop]]s.

SoC [[peripheral]]s including [[counter (digital)|counter]]-timers, real-time [[timer]]s and [[power-on reset]] generators. SoCs also include [[voltage regulator]]s and [[power management]] circuits.

=== Intermodule communication ===
SoCs comprise many [[execution unit]]s. These units must often send data and [[Instruction (computing)|instructions]] back and forth. Because of this, all but the most trivial SoCs require [[Communications system|communications subsystems]]. Originally, as with other [[microcomputer]] technologies, [[Bus (computing)|data bus]] architectures were used, but recently designs based on sparse intercommunication networks known as [[Network on a chip|networks-on-chip]] (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in the near future.<ref name=":0">{{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last1=Kundu|first1=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=978-1-4665-6527-2|edition=1st|location=Boca Raton, FL|oclc=895661009}}</ref>

==== Bus-based communication ====
Historically, a shared global [[bus (computing)|computer bus]] typically connected the different components, also called "blocks" of the SoC.<ref name=":0" /> A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture ([[Advanced Microcontroller Bus Architecture|AMBA]]) standard.

[[Direct memory access]] controllers route data directly between external interfaces and SoC memory, bypassing the CPU or [[control unit]], thereby increasing the data [[throughput]] of the SoC. This is similar to some [[device driver]]s of peripherals on component-based [[multi-chip module]] PC architectures.

Wire delay is not scalable due to continued [[miniaturization]], [[Computer performance|system performance]] does not scale with the number of cores attached, the SoC's [[operating frequency]] must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power. These challenges are prohibitive to supporting [[Manycore processor|manycore]] systems on chip.<ref name=":0" />{{Rp|xiii}}

==== Network on a chip ====
{{Main|Network on a chip}}
In the late 2010s, a trend of SoCs implementing [[communications subsystem]]s in terms of a network-like topology instead of [[bus (computing)|bus-based]] protocols has emerged. A trend towards more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.<ref name=":0" />{{Rp|xiii}} This has led to the emergence of interconnection networks with [[Router (computing)|router]]-based [[packet switching]] known as "[[network on a chip|networks on chip]]" (NoCs) to overcome the [[Bottleneck (engineering)|bottlenecks]] of bus-based networks.<ref name=":0" />{{Rp|xiii}}

Networks-on-chip have advantages including destination- and application-specific [[routing]], greater power efficiency and reduced possibility of [[bus contention]]. Network-on-chip architectures take inspiration from [[communication protocols]] like [[Transmission Control Protocol|TCP]] and the [[Internet protocol suite]] for on-chip communication,<ref name=":0" /> although they typically have fewer [[network layer]]s. Optimal network-on-chip [[network architecture]]s are an ongoing area of much research interest. NoC architectures range from traditional distributed computing [[Network topology|network topologies]] such as [[Torus interconnect|torus]], [[Hypercube internetwork topology|hypercube]], [[Mesh networking|meshes]] and [[tree network]]s to [[genetic algorithm scheduling]] to [[randomized algorithm]]s such as [[Branching random walk|random walks with branching]] and randomized [[time to live]] (TTL).

Many SoC researchers consider NoC architectures to be the future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited [[Floorplan (microelectronics)|floorplanning]] choices as the number of cores in SoCs increase, so as [[three-dimensional integrated circuit]]s (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs.<ref name=":0" />