Editing S/PDIF (section)

==Limitations==
The receiver does not control the data rate, so it must avoid [[bit slip]] by synchronizing its reception with the source clock. Many S/PDIF implementations cannot fully decouple the final signal from influence of the source or the interconnect. Specifically, the process of [[clock recovery]] used to synchronize reception may produce [[jitter]].<ref name="pozzoli">Giorgio Pozzoli. "[http://www.tnt-audio.com/clinica/diginterf1_e.html DIGITabilis: crash course on digital audio interfaces]" tnt-audio.com.</ref><ref name="dunn_hawksford">Chris Dunn, Malcolm J. Hawksford. "[http://www.aes.org/e-lib/browse.cfm?elib=6773 Is the AES/EBU/SPDIF Digital Audio Interface Flawed?]" AES Convention 93, paper 3360.</ref><ref name="tracy">{{cite web|archive-url=https://web.archive.org/web/20170701142216/http://www.audiocraftersguild.com/AandE/npt.on.jitter2.htm|archive-date=1 July 2017|first=Norman|last=Tracy|url=http://www.audiocraftersguild.com/AandE/npt.on.jitter2.htm|title=On Jitter, the S/PDIF Standard, and Audio DACs.}}</ref> If the [[digital-to-analog converter|DAC]] does not have a stable clock reference then noise will be introduced into the resulting analog signal. However, receivers can implement various strategies that limit this influence.<ref name="tracy" /><ref name="Lesso">{{cite journal|first=Paul|last=Lesso|url=http://www.wolfsonmicro.com/documents/uploads/misc/en/A_high_performance_SPDIF_receiver_Oct_2006.pdf|archive-url=https://web.archive.org/web/20140604060307/http://www.wolfsonmicro.com/documents/uploads/misc/en/A_high_performance_SPDIF_receiver_Oct_2006.pdf|archive-date=4 June 2014|title=A High Performance S/PDIF Receiver|publisher=Audio Engineering Society|year=2006}} AES Convention 121, paper 6948</ref>